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MAX11253 Datasheet, PDF (40/51 Pages) Maxim Integrated Products – Longer Battery Life for Portable Applications
MAX11253
16-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,
Delta-Sigma ADC with SPI Interface
STAT: Status Register (Read) (continued)
BIT NAME
SYSGOR
DESCRIPTION
This bit is set to ‘1’ to indicate that a system gain calibration results in an overrange condition of the calibration
coefficient. The SCGC calibration coefficient is set to the maximum value of 1.9999999.
DOR
This bit is set to ‘1’ to indicate that the conversion result has exceeded the maximum or minimum value of the
converter and that the result has been clipped or limited to the maximum or minimum value. When set to ‘0’
the conversion result is within the full-scale range of the inputs.
AOR
This bit is set to ‘1’ to indicate that the modulator detected an analog overrange condition by having the input
signal level greater than the reference voltage. This check for overrange includes the PGA gain.
RATE[3:0]
These bits indicate the conversion rate that corresponds to the result in the DATA registers or the rate that was
used for calibration coefficient calculation. The corresponding RATE[3:0] is only valid until the DATA registers
are read. The decoding of RATE[3:0] is shown in Table 1.
PDSTAT[1:0]
These bits indicate the state of the MAX11253. See Table 6 for transition times.
PDSTAT1 PDSTAT0
DESCRIPTION
0
0
CONVERSION
0
1
SLEEP
1
0
STANDBY (default)
1
1
RESET
MSTAT
This bit is set to ‘1’ to indicate when a signal measurement is in progress. This indicates that a conversion,
self-calibration, or system calibration is in progress and that the modulator is busy. When the modulator is not
converting, this bit will be set to ‘0’.
RDY
This bit is set to ‘1’ to indicate that a new conversion result is available in sequencer mode 1. A complete read
of the corresponding DATA register will reset this bit to ‘0’. This bit is invalid in sequencer mode 2 or 3. The
function of this bit is redundant and is duplicated by the RDYB pin.
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