MAX11253 Datasheet, PDF (27/51 Pages) Maxim Integrated Products – Longer Battery Life for Portable Applications

MAX11253
SPI Command Sequence
SPI Transactions
CSB=0; SPI=0xD012; CSB=1;
CSB=0; SPI=0xCAF000; CSB=1;
CSB=0; SPI=0xC65C; CSB=1;
CSB=0; SPI=0xCE0B274F; CSB=1
CSB=0; SPI=0xC43F; CSB=1;
CSB=0; SPI=0xBE; CSB=1;
Wait
CSB=0; SPI=0xD30000; CSB=1;
Wait
CSB=0; SPI=0xD50000; CSB=1;
Wait
CSB=0; SPI=0xD10000; CSB=1;
STOP
16-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,
Delta-Sigma ADC with SPI Interface
Description
Write to SEQ register
Set MUX to 0b000, MODE to 0b10, GPODREN to
0b0, MDREN to 0b1, RDYBEN to 0b0
Write to DELAY register
Set MUX[7:0] to 0xF0, GPO[7:0] to 0x00
Write to CTRL3 register
Set GPO_MODE to 0b1, all others to the
default value;
Write to CHMAP0 register
CH2=0x0B: CH2_GPO=0b00, CH2_ORD=0b010,
CH2_EN=0b1, CH2_GPOEN=0b1
CH1=0x27: CH1_GPO=0b01, CH1_ORD=0b001,
CH1_EN=0b1, CH1_GPOEN=0b1
CH0=0x4F: CH0_GPO=0b10,
CH0_ORD=0b011, CH0_EN=0b1, CH0_GPOEN=0b1
Write to CTRL2 register
set PGA gain to 0b111, LDOEN=0b1,
LPMODE=0b1, PGAEN=0b1;
Convert using sequencer mode, data rate
selected is 6,400 sps;
RDYB negative edge transition from ‘1’ to
‘0’ indicates conversion completed and
DATA register ready for read
Read register DATA1;
RDYB negative edge transition from ‘1’ to
‘0’ indicates conversion completed and
DATA register ready for read
Read register DATA2
RDYB negative edge transition from ‘1’ to
‘0’ indicates conversion completed and
DATA register ready for read
Read register DATA0;
Mode activity is completed. The MAX11253
powers down into SLEEP state waiting for
the next command
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