MAX11253 Datasheet, PDF (31/51 Pages) Maxim Integrated Products – Longer Battery Life for Portable Applications

MAX11253
16-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,
Delta-Sigma ADC with SPI Interface
Power-Down States
To reduce overall power consumption, the MAX11253
features two power-down states: STANDBY and SLEEP.
In SLEEP mode all circuitry is powered down, and the
supply currents are reduced to leakage currents. In
STANDBY mode the internal LDO and a low-frequency
oscillator are powered up to enable fast startup. After
POR or a hardware reset the MAX11253 is in STANDBY
mode until a command is issued.
Changing Power-Down States
Mode transition times are dependent on the current mode
of operation. STAT:PDSTAT is updated at the end of all
mode changes and is a confirmation of a completed trans-
action. The MAX11253 does not use a command FIFO or
queue. The user must confirm the completed transaction
by polling STAT:PDSTAT after the expected delay, as
described in Table 6. Once the transition is complete, it is
safe to send the next command.
Verify that STAT:PDSTAT indicates the desired state
before issuing a conversion command.
Writes to any CTRL register during a conversion aborts
the conversion and returns the MAX11253 to STANDBY
state.
SLEEP STATE TO STANDBY STATE (FAST)
1) Set CTRL1:PD[1:0] = ‘10’ for STANDBY state.
2) Set SEQ:MODE[1:0] = ‘00’ for sequencer mode 1
3) Issue a conversion command with MODE[1:0] set to
‘11’.
4) Monitor STAT:PDSTAT[1:0] = ‘00’ for active state.
5) Write the conversion command with MODE[1:0] set to
‘01’.
6) Monitor STAT:PDSTAT = ‘10’ for completion.
STANDBY STATE TO SLEEP STATE (FAST)
1) Set CTRL1:PD[1:0] = ‘01’ for STANDBY state.
2) Set SEQ:MODE[1:0] = ‘00’ for sequencer mode 1
3) Issue a conversion command with MODE[1:0] set to
‘11’.
4) Monitor STAT:PDSTAT[1:0] = ‘00’ for active state.
5) Write the conversion command with MODE[1:0] set to
‘01’.
6) Monitor STAT:PDSTAT = ‘01’ for completion.
Calibration
Two types of calibration are available: self calibration
and system calibration. Self calibration is used to reduce
the MAX11253’s gain and offset errors during changing
operating conditions such as supply voltages, ambi-
ent temperature, and time. System calibration is used
to reduce the gain and offset error of the entire signal
path. This enables calibration of board level components
and the integrated PGA. System calibration requires the
MAX11253’s inputs to be reconfigured for zero scale and
full scale during calibration. The GPO/GPIO pins can be
used for this purpose. See Figure 17 for details of the
calibration signal flow.
The calibration coefficients are stored in the registers
SCOC, SCGC, SOC and SGC. Data written to these
registers is stored within the SPI domain and copied to
internal registers before a conversion starts to process
the raw data (see Figure 17). An internal or system cali-
bration only updates the internal register values and does
not alter the contents stored in the SPI domain. The bit
CTRL3:CALREGSEL decides whether the internal con-
tents or the contents stored in the SPI domain are read
back during a read access of these registers.
COMMAND LATCHED
RESET COMMAND
STAT:INRESET
STAT:PDSTAT = ‘00’/’10'
SERIAL INTERFACE IS READ
ONLY DURING THIS PERIOD
IDLE
‘11’
SERIAL INTERFACE IS
AVAIABLE FOR BOTH
READ AND WRITE
‘10’
Figure 16. STAT:INRESET and STAT:PDSTAT Timing
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