MAX11253 Datasheet, PDF (22/51 Pages) Maxim Integrated Products – Longer Battery Life for Portable Applications

MAX11253
16-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,
Delta-Sigma ADC with SPI Interface
Modes and Registers
The MAX11253 interface operates in two fundamental
modes, either to issue a conversion command or to
access registers. The mode of operation is selected by a
command byte. Every SPI transaction to the MAX11253
starts with a command byte. The command byte begins
with the MSB (B7) set to ‘1’. The next bit (B6) determines
whether a conversion command is sent or register read/
write access is requested.
During a register read/write access, hold CSB low for the
entire read or write operation and pull CSB high at the
end of the command. For example, if the command is to
read a 16-bit data register, hold CSB low for 24 SCLK
cycles (8 cycles for the command byte plus 16 cycles
for the data). CSB transitions must not occur near the
rising edge of SCLK and must conform to the setup and
hold timing detailed in the timing section. See SPI Timing
Requirements table.
Command Byte
The conversion command sets the mode of operation
(conversion, calibration, or power-down) as well as the
conversion speed of the MAX11253. The register read/
write command specifies the register address as well as
the direction of the access (read or write).
Channel Sequencing
Changing SEQUENCER Modes
Mode Exit (See Table 8. Register Map for Register
Definitions)
To exit any of the three sequencer modes at any time
program the following sequence:
1) Issue a power-down command to exit the conver-
sion process to STANDBY or SLEEP, as defined in
CTRL1:PD[1:0]:
a. Write a conversion command byte (see Table 4.
Command Byte Definition) and set MODE[1:0] of
the command byte to ‘01’
2) Wait for STAT:PDSTAT[1:0] = ‘01’ (SLEEP) or
STAT:PDSTAT[1:0] = ‘10’ (STANDBY).
Note: For all sequencer modes, the default exit state
upon completion of all conversions is SLEEP. In
sequencer mode 1, however, continuous conversion
operation (CTRL1:SCYCLE=’0’) and continuous sin-
gle-cycle conversion operation (CTRL1:SCYCLE=’1’
and CTRL1:CONTSC=’1’) are running continuously
and must be terminated with the Mode Exit sequence.
Table 4. Command Byte Definition
B7 (MSB)
B6
Conversion Command
1
0
Register Read/Write
1
1
B5
MODE1
RS4
B4
MODE0
RS3
B3
RATE3
RS2
B2
RATE2
RS1
B1
RATE1
RS0
B0
RATE0
R/W
Table 5. Command Byte Decoding
BIT NAME
MODE[1:0]
RATE[3:0]
RS[4:0]
R/W
DESCRIPTION
The MODE bits are used to set the functional operation of the MAX11253 according to the following decoding.
MODE1 MODE0
DESCRIPTION
0
0
Unused
0
1
Power-down performed based on the CTRL1:PD[1:0] setting
1
0
Calibration performed based on the CTRL1:CAL[1:0] setting
1
1
Sequencer mode. The operation is based on the configuration of the SEQ register
These bits determine the conversion speed of the MAX11253. The decoding is shown in Table 1.
Register address as shown in Table 8.
The R/W bit enables either a read or a write access to the address specified in RS[4:0]. If R/W is set to ‘0’, then data
is written to the register. If the R/W bit is set to ‘1’, then data is read from the register.
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