MAX11253 Datasheet, PDF (21/51 Pages) Maxim Integrated Products – Longer Battery Life for Portable Applications

MAX11253
16-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,
Delta-Sigma ADC with SPI Interface
SPI 8b REGISTER READ
RDYB
tCSS0
CSB
‘X’
tCSH1
tCSW
SCLK
tCH
1
tDS
tCL
tCP
8
tDH
tCSS1
16 _{8b data}
DIN
‘X’
‘1’ ‘1’ RS4 RS3 RS2 RS1 RS0 ‘1’ ‘X’ ‘X’ ‘X’ ‘X’ ‘X’ ‘X’ ‘X’ ‘X’
‘X’
tDOE
DOUT ^HIGH-Z
‘X’
tDOT
tDOH
D7 D6 D5 D4 D3 D2 D1 D0
tDOD
HIGH-Z
Figure 7. SPI Register Read Timing Diagram. For read patterns, the user may latch the MAX11253 output data on either rising edges
(9–16) running at minimum latency or falling edges 9–16 running at increased latency.
SPI 24B DATA READ
RDYB
tCSS0
CSB
tCH
tCL
tCP
SCLK
1
89
tDS
tDH
DIN
‘X’ ‘1’ ‘1’ ‘0’ ‘0’ ‘1’ ‘1’ ‘0’ ‘1’
tDOE
DOUT ^HIGH-Z
‘X’
tDOT
MSB
tR1
tCSH1
tCSW
tCSS1
31 24b data
tDOH
LSB
tDOD
HIGH-Z
Figure 8. SPI DATA Readout Timing Diagram
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