MAX11253 Datasheet, PDF (28/51 Pages) Maxim Integrated Products – Longer Battery Life for Portable Applications

MAX11253
16-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,
Delta-Sigma ADC with SPI Interface
Power-On Reset and Undervoltage Lockout
A global power-on reset (POR) is triggered until AVDD,
DVDD, and CAPREG cross a minimum threshold voltage
(V_LH), as shown in Figure 13.
To prevent ambiguous power-supply conditions from
causing erratic behavior, voltage detectors monitor AVDD,
DVDD, and CAPREG and hold the MAX11253 in reset
when supplies fall below V_HL (see Figure 13). The ana-
log undervoltage lockout (AVDD UVLO) prevents the
ADC from converting when AVDD falls below V_HL. The
CAPREG UVLO resets and prevents the low-voltage
digital logic from operating at voltages below V_HL. DVDD
UVLO thresholds supersede CAPREG thresholds when
CAPREG is externally driven. Figure 14 shows a flow dia-
gram of the POR sequence. Glitches on supplies AVDD,
DVDD, and CAPREG for durations shorter than T_P are
suppressed without triggering POR or UVLO. For glitch
durations longer than T_P, POR is triggered within T_DEL
seconds. See the Electrical Characteristics table for val-
ues of V_LH, V_HL, T_P, and T_DEL.
Power-On Reset Timing
Power-on reset is triggered during power-up and under-
voltage conditions as described above. Completion of the
POR process is monitored by polling STAT:PDSTAT[1:0]
= ‘10’ for STANDBY state (see Figure 15).
Reset
Hardware Reset Using RSTB
The MAX11253 features an active-low RSTB pin to per-
form a hardware reset. Pulling the RSTB pin low stops
any conversion in progress, reconfigures the internal
registers to the power-on reset state and resets all digital
filter states to zero. After the reset cycle is completed, the
MAX11253 remains in STANDBY state and awaits further
commands.
Software Reset
The host can issue a software reset to restore the default
state of the MAX11253. A software reset sets the interface
registers back into their default states and resets the inter-
nal state machines. However, a software reset does not
emulate the complete POR or hardware reset sequence.
Two SPI transactions are required to issue a software
reset: First set CTRL1:PD[1:0] to ‘11’ (RESET). Then
issue a conversion command with MODE[1:0] set to ‘01’.
To confirm the completion of the reset operation,
STAT:PDSTAT and STAT:INRESET must be monitored.
Figure 16 shows the state transition for the RESET com-
mand and the relative timing of STAT register update.
During reset, INRESET = ’1’ and PDSTAT= ‘11’. The
SPI interface cannot be written until MAX11253 enters
STANDBY state where PDSTAT = ‘10’. To confirm com-
pletion of the RESET command, monitor for INRESET =
‘0’ and PDSTAT = ‘10’.0 Table 6 summarizes the maxi-
mum delay for reset operation.
AVDD
DVDD
VLH
CAPREG
PORB
VHYS
VHL
TP
TDEL
TP
TDEL
Figure 13. Undervoltage Lockout Characteristic Voltage Levels and Timing
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