MAX11253 Datasheet, PDF (15/51 Pages) Maxim Integrated Products – Longer Battery Life for Portable Applications

MAX11253
16-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,
Delta-Sigma ADC with SPI Interface
Programmable Gain Amplifier (PGA)
The integrated PGA provides gain settings from 1x to
128x. (Figure 2). Direct connection is available to bypass
the PGA and directly connect to the modulator. The PGA’s
absolute input voltage range is CMI_RNG and the PGA
output voltage range is VOUT_RNG, as specified in the
Electrical Characteristics.
Note that linearity and performance degrade when the
specified input common-mode voltage of the PGA is
exceeded. The input common-mode range and output
common-mode range are shown in Figure 3. The fol-
lowing equations describe the relationship between the
analog inputs and PGA output.
AINP = Positive input to the PGA
AINN = Negative input to the PGA
CAPP = Positive output of PGA
CAPN = Negative output of PGA
V_CM = Input common mode
GAIN = PGA gain
V_REF = ADC reference input voltage
V_IN = V_AINP - V_AINN
Note: Input voltage range is limited by the reference volt-
age as described by V_IN ≤ ±V_REF/GAIN
V_CM
=
(V_AINP
+
2
V_AINN)
V_CAPP =V_CM + GAIN × (V_AINP − V_CM)
= V_CAPN V_CM − GAIN × (V_CM − V_AINN)
AINP
A1
Input Voltage Range
The ADC input range is programmable for bipolar (-V_REF
to +V_REF) or unipolar (0 to V_REF) ranges. The U/B bit in
the CTRL1 register configures the MAX11253 for unipolar
or bipolar transfer functions.
Data Rates
Table 1 lists the available data rates for the MAX11253,
RATE[3:0] setting of the conversion command (see the
Modes and Registers section). The single-cycle mode has
an overhead of 48 digital master clocks that is approxi-
mately 5.86µs for a typical digital master clock frequency
of 8.192MHz. The single-cycle effective column contains
the data rate values including the 48 clock startup delays.
The 48 clocks are required to stabilize the modulator at
startup. In continuous conversion mode, the output data
rate is five times the single-cycle rate up to a maximum
of 64ksps. During continuous conversions, the output
sample data requires five 24-bit cycles to settle to a valid
conversion from an input step, PGA gain changes, or a
change of input channel through the multiplexer.
If self-calibration is used, 48 additional master clocks are
required to process the data per conversion. Likewise,
system calibration takes an additional 48 master clocks to
complete.
If both self and system calibration are used, it takes an
additional 80 master clocks to complete. If self and/or
system calibration are used, the effective data rate will be
reduced by these additional clock cycles per conversion.
Noise Performance
The MAX11253 provides exceptional noise performance.
SNR is dependent on data rate, PGA gain, and power
mode. Bandwidth is reduced at low data rates; both noise
and SNR are improved proportionally. Tables 2 and 3
summarize the noise performance for both single-cycle
and continuous operation versus data rate, PGA gain, and
power mode.
R3
CAPP
R1
R2
R1
CCAPP/N
(C0G capacitor)
A2
AINN
Figure 2. Simplified Equivalent Diagram of the PGA
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R3
CAPN
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