MAX11253 Datasheet, PDF (19/51 Pages) Maxim Integrated Products – Longer Battery Life for Portable Applications

MAX11253
16-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,
Delta-Sigma ADC with SPI Interface
For sequencer mode 2 and sequencer mode 3, the
RDYB behavior for a multichannel conversion can be
controlled by the SEQ:RDYBEN bit. The default value
of SEQ:RDYBEN is ‘0’. When set to ‘0’, RDYB behaves
the same for multichannel conversion and single chan-
nel operation. The RDYB toggles high to low after each
channel is ready to update its corresponding data register.
After the channel data is read, the RDYB will reset back
to ‘1’. If the channel data is not read and the next chan-
nel is ready to update its data, the RDYB will toggle low
to high four cycles before the data update (similar to a
single channel operation), and then toggle high to low
indicating the new channel’s conversion data is available.
If ‘N’ channels are enabled, RDYB will toggle high to low
‘N’ times. If SEQ:RDYBEN is set to ‘1’, the RDYB event
for each channel is suppressed. The RDYB toggles high
to low when the last channel is ready to update its corre-
sponding data register and a single high to low transition
happens.
The STAT:SRDY[5:0] bits get set to ‘1’ when their corre-
sponding channel finishes converting, irrespective of the
RDYBEN setting for sequencer modes 2 and 3. The con-
version status is available by reading the STAT:MSTAT bit.
This stays high as long as the modulator is converting.
See Figure 4 for timing of RDYB.
SPI Incomplete Write Command Termination
In case of register writes, the register values get updated
every 8th clock cycle with a byte of data starting from
the MSB. A minimum of 16 SCLKs are needed to write
the first byte of data in a multibyte register or for an 8-bit
register. For example, a 24-bit register write requires
8 SCLKs for register access byte and 24 SCLKs (data
bits to be written). If only 15 SCLKs were issued out of
the 32 expected, the register value will not be updated.
At least 16 SCLKs are required to update the MSB byte.
For example, when the user issues a write command for
a 24-bit register write and terminates after 16 SCLKs, only
the MSB byte, bits 23 to 16 of the register are updated.
Bits 15 to 0 retain the old value of the register.
SPI Incomplete Read Command Termination
The SPI interface stays in read mode for as long as CSB
stays low independent of the number of SCLKs issued.
The CSB pin must be toggled high to remove the device
from the bus and reset the internal SPI controller. Any
activity on the DIN pin is ignored while in the register read
mode. The read operation is terminated if the CSB pin is
toggled high before the maximum number of SCLKs is
issued.
When reading from DATA registers, the behavior of RDYB
will depend on how many bits are read. If at least 23 bits
are read, the read operation is complete and RDYB resets
to high. If the user reads less than 23 bits, internally the
logic considers the read incomplete, and RDYB stays low.
The user can initiate a new read within the same conver-
sion cycle; however, the new 24-bit read must complete
before the next DATA register update.
SPI Timing Characteristics
The SPI timing diagrams illustrating command byte and
register access operations are shown in Figure 5 to
Figure 8. The MAX11253 timing allows for the input data
to be changed by the user at both rising and falling edges
of SCLK. The data read out by the device on SCLK falling
edges can be sampled by the user on subsequent rising
or falling edges.
CSB/SCLK/DIN
SCYCLE=’1',
CONTSC=’0'
RDYB
SCYCLE=’1',
CONTSC=’1'
RDYB
SCYCLE=’0',
CONTSC=’x'
RDYB
CONVERT COMMANDS
N × tCNV
DATA not retrieved
tCNV
N × tCNV
DATA
RETRIEVED
5 tCNV
tCNV
Figure 4. Timing of RDYB in All Conversion Configurations: Single-Cycle, Single-Cycle Continuous, and Continuous. In sequencer
mode 1 and in sequencer modes 2 and 3, with SEQ:RDYBEN=’0’ N = 1. In sequencer modes 2 and 3 with SEQ:RDYBEN=’1’ N =
number of active channels.
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