MAX11253 Datasheet, PDF (42/51 Pages) Maxim Integrated Products – Longer Battery Life for Portable Applications

MAX11253
16-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,
Delta-Sigma ADC with SPI Interface
CTRL2: Control Register 2 (Read/Write)
BIT NAME
DEFAULT
Default = 0x20
EXTCLK
CSSEN
0
0
LDOEN
1
LPMODE
0
PGAEN
0
PGAG2
0
PGAG1
0
PGAG0
0
This register controls the selection and configuration of optional functions.
BIT NAME
EXTCLK
CSSEN
LDOEN
LPMODE
PGAEN
PGA[2:0]
DESCRIPTION
External clock mode is enabled by setting this bit to ‘1’. In this mode, the internal oscillator is bypassed
and the GPIO0/CLK pin is configured as external clock input.
Setting this bit to ‘1’ enables the current source and current sink on the analog inputs to detect sensor
opens or shorts.
Set this bit to ‘1’ to enable the internal LDO. Set this bit to ‘0’ when driving the CAPREG pin externally
with a 1.8V supply. When driving the CAPREG pin with external supply, the user must ensure that the
CAPREG pin is connected to the DVDD pin.
PGA low-power mode is enabled by setting this bit to ‘1’. The PGA operates with reduced power
consumption and reduced performance. The LPMODE does not affect power or performance when
the PGA is not enabled.
The PGA enable bit controls the operation of the PGA. A ‘1’ enables and a ‘0’ disables the PGA.
The ‘PGA’ bits control the PGA gain. The PGA gain is set by:
PGA2 PGA1 PGA0
DESCRIPTION
0
0
0 Gain = 1
0
0
1 Gain = 2
0
1
0 Gain = 4
0
1
1 Gain = 8
1
0
0 Gain = 16
1
0
1 Gain = 32
1
1
0 Gain = 64
1
1
1 Gain = 128
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