MAX11253 Datasheet, PDF (26/51 Pages) Maxim Integrated Products – Longer Battery Life for Portable Applications

MAX11253
16-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,
Delta-Sigma ADC with SPI Interface
Operating Examples—From Full Power-Down to
Mode 3
In this example, channels 0, 1, and 2 are configured for
conversion in mode 3. Channel 0 is configured last in the
scan order and the GPIO0 is mapped to this channel.
Channel 1 is configured first in the scan order and GPO1
is mapped to this channel. Channel 2 is configured sec-
ond in the scan order and GPO0 is mapped to this chan-
nel. Channels 0, 1, and 2 are enabled for scan and GPO/
GPIO switching is also enabled. The RDYBEN is not set
which generates a RDYB transition after each channel is
converted. The PGA is configured for a gain of 128 and
the data rate is 6,400sps in single-cycle mode. The MUX
delays are enabled for all used channels and the GPO/
GPIO delays are disabled. Reference SPI Command
Sequence section.
Error Checking Sequencer Mode 3
The MAX11253 perform checks on registers CHMAP0 and
CHMAP1. Error flags are set when invalid values are set:
STAT:GPOERR is set when more than one input chan-
nel is mapped to the same GPO/GPIO pin.
STAT:ORDERR is set when CHn_ORD is set
as ‘000’ or ‘111’ and channel n is enabled using
CHMAPx:CHn_EN.
Supplies and Power-On Sequence
The MAX11253 requires two power supplies, AVDD and
DVDD. These power supplies can be sequenced in any
order. The analog supply (AVDD) powers the analog
inputs and the modulator. The DVDD supply powers the
SPI interface. The low-voltage core logic can either be
powered by the integrated LDO (default) or via DVDD.
Figure 12 shows the two possible schemes. CAPREG
denotes the internally generated supply voltage. If the
LDO is used, the DVDD operating voltage range is from
2.0V to 3.6V. If the core logic is directly powered by DVDD
(DVDD and CAPREG connected together), the DVDD
operating voltage range is from 1.7V to 2.0V.
DVDD OPERATING BETWEEN 2.0V TO 3.6V
LDO ENABLED (SET CTRL2:LDOEN = ‘1’) AND BYPASS
CAPREG TO DGND WITH 220nF
AVDD
DVDD
LDO
MAX11253
DVDD OPERATING BETWEEN 1.7V TO 2.0V
LDO DISABLED (SET CTRL2:LDOEN = ‘0’) AND
CONNECT CAPREG TO DVDD AT BOARD LEVEL
AVDD
DVDD
LDO
MAX11253
ANALOG
2V DIGITAL
LOGIC
DIGITAL
INTERFACE
INPUTS
AND
OUTPUTS
ANALOG
2V DIGITAL
LOGIC
DIGITAL
INTERFACE
INPUTS
AND
OUTPUTS
CAPREG
220nF
0603
X7R
DGND
Figure 12. MAX11253 Digital Power Architecture
CAPREG
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