MAX11253 Datasheet, PDF (30/51 Pages) Maxim Integrated Products – Longer Battery Life for Portable Applications

MAX11253
16-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,
Delta-Sigma ADC with SPI Interface
POWER-ON
NO
AVDD UVLO
TRIGGERED?
YES
NO _{CAPREG UVLO}
TRIGGERED?
YES
NO
DVDD UVLO
TRIGGERED?
YES
ANALOG
RESET
OSCILLATOR
RESET
Figure 14. MAX11253 UVLO and POR Flow Diagram
POWER-ON
RESET FOR 2V
DIGITAL LOGIC
POWER-ON RESET
FOR DIGITAL LOGIC
AND INTERFACE
VDVDD
IN POWER-ON RESET
SERIAL
INTERFACE
READ ONLY
OUT OF POWER-ON RESET
SERIAL INTERFACE AVAILABLE FOR BOTH READ AND WRITE
STAT:PDSTAT=’XX’
‘11’
‘10’ (STANDBY)
Figure 15. Power-On Reset and PDSTAT Timing
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