MAX11253 Datasheet, PDF (18/51 Pages) Maxim Integrated Products – Longer Battery Life for Portable Applications

MAX11253
16-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,
Delta-Sigma ADC with SPI Interface
Table 3. Noise vs. PGA Mode and Gain (Continuous Conversion)
CONTINUOUS CONVERSION MODE
INPUT-REFERRED NOISE VOLTAGE (µVRMS) vs. PGA GAIN SETTING
DATA
RATE
(sps)
1
LP LN
2
LP LN
4
LP LN
8
LP LN
16
LP LN
32
LP LN
64
LP LN
128
LP LN
15.6
31.2
62.5
125
250
500
1000
2000
4000
8000
16000
32000
64000
31.72 31.72 15.86 15.86 7.93 7.93 3.96 3.96 1.98 1.98 0.99 0.99 0.50 0.50 0.25 0.25
31.72 31.72 15.86 15.86 7.93 7.93 3.97 3.96 1.98 1.98 0.99 0.99 0.50 0.50 0.25 0.25
31.72 31.72 15.86 15.86 7.93 7.93 3.97 3.96 1.98 1.98 0.99 0.99 0.50 0.50 0.25 0.25
31.73 31.72 15.86 15.86 7.93 7.93 3.97 3.97 1.98 1.98 0.99 0.99 0.50 0.50 0.26 0.25
31.74 31.73 15.87 15.86 7.93 7.93 3.97 3.97 1.99 1.98 1.00 0.99 0.51 0.50 0.27 0.26
31.75 31.73 15.88 15.87 7.94 7.93 3.97 3.97 1.99 1.99 1.00 1.00 0.52 0.51 0.29 0.27
31.78 31.75 15.89 15.87 7.95 7.94 3.98 3.97 2.00 1.99 1.02 1.00 0.54 0.52 0.33 0.29
31.83 31.77 15.92 15.89 7.97 7.95 3.99 3.98 2.01 2.00 1.04 1.02 0.58 0.54 0.39 0.32
31.93 31.82 15.97 15.91 8.00 7.96 4.02 3.99 2.04 2.01 1.08 1.04 0.64 0.57 0.48 0.38
32.04 31.88 16.03 15.95 8.03 7.98 4.05 4.01 2.07 2.03 1.12 1.06 0.72 0.62 0.58 0.45
32.14 31.93 16.08 15.97 8.07 8.00 4.07 4.02 2.10 2.04 1.16 1.08 0.76 0.64 0.65 0.50
32.61 32.19 16.35 16.11 8.23 8.08 4.18 4.08 2.22 2.11 1.31 1.16 0.99 0.79 0.89 0.66
34.51 33.19 16.99 16.45 8.57 8.26 4.41 4.20 2.42 2.21 1.56 1.31 1.32 1.00 1.19 0.87
LP = Low Power, LN = Low Noise
Serial Interface
The MAX11253 interface is fully compatible with SPI,
QSPI™, and MICROWIRE®-standard serial interfaces.
The SPI interface provides access to on-chip registers
that are 8 bits to 24 bits wide. The interface consists of
the standard SPI signals CSB, SCLK, DIN, and DOUT. An
additional RDYB output signals data availability.
CSB (Chip Select)
CSB is an active-low chip-select input to communicate
with the MAX11253. CSB transitioning from low to high
is used to reset the SPI interface. When CSB is low, data
is clocked into the device from DIN on the rising edge of
SCLK. Data is clocked out of DOUT on the falling edge of
SCLK. When CSB is high, SCLK and DIN are ignored and
DOUT is high impedance, allowing DOUT to be shared
with other devices.
SCLK (Serial Clock)
The SCLK is used to synchronize data communication
between the host device and the MAX11253. Data is
shifted in on the rising edge of SCLK and data is shifted
out on the falling edge of SCLK. SCLK remains low when
not active.
DIN (Serial Data Input)
Data present on DIN is clocked into internal registers on
the rising edge of SCLK.
DOUT (Serial Data Output)
The DOUT pin is actively driven when CSB is low and
high impedance when CSB is high. Data is shifted out on
DOUT on the falling edge of SCLK.
RDYB (Data Ready)
RDYB indicates the ADC conversion status and the avail-
ability of the conversion result. When RDYB is low, a
conversion result is available. When RDYB is high, a con-
version is in progress and the data for the current conver-
sion is not available. RDYB is driven high after a complete
read of the data register. RDYB resets to high four master
clock cycles prior to the next DATA register update.
If data was read, then RDYB transitions from high to
low at the output data rate. If the previous data was not
read, then the RDYB transitions from low to high for four
master clock cycles and then transitions from high to low.
In continuous mode, RDYB remains high for the first four
conversion results and on the 5th result, RDYB goes low.
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corporation.
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