English
Language : 

LTC3730_15 Datasheet, PDF (9/28 Pages) Linear Technology – 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller
W
FU CTIO AL DIAGRA
LTC3730
PLLIN
FIN
50k
RLP PLLFLTR
CLP
PHASE DET
OSCILLATOR
CLK1
CLK2
CLK3
PGOOD
FCB
+
0.6V –
100µs
DELAY
PROTECTION
IN+
FCB
0.66V
EAIN
0.54V
IN–
–
A1
+
AMPOUT
R1
20k
EAIN
VFB
0.600V
–
EA
+
OV
+
0.660V
–
ITH
CC
R2 VARIABLE
RC
5-BIT VID DECODER
VID0 VID1 VID2 VID3 VID4
DUPLICATE FOR SECOND AND THIRD
CONTROLLER CHANNELS
BOOST
RS
LATCH
DROP
OUT
DET
SQ
RQ
B
0.55V
BOT
TG
TOP
FORCE BOT
FCB
SHDN
SWITCH
LOGIC
VCC
BOT
SW
BG
PGND
VCC
VIN
DB
CB
+
CIN
I1 – +
SLOPE
COMP
5(VFB)
0.86V
SS
CLAMP 2.4V
3mV
54k
–
I2
+
54k
L
VCC
36k SENSE+
36k SENSE–
RSENSE
COUT
VOUT
VCC
SHDN
1.5µA RST
5(VFB)
6V
SHED
0.600V
RUN
SOFT-
START
INTERNAL
SUPPLY
UV RESET
Figure 2
VREF
VCC
SGND
VCC
+
CCC
RUN/SS
CSS
3730 F02
U
OPERATIO (Refer to Functional Diagram)
Main Control Loop
The IC uses a constant frequency, current mode step-
down architecture. During normal operation, each top
MOSFET is turned on each cycle when the oscillator sets
the RS latch, and turned off when the main current
comparator, I1, resets each RS latch. The peak inductor
current at which I1 resets the RS latch is controlled by the
voltage on the ITH pin, which is the output of the error
amplifier EA. The EAIN pin receives a portion of this
voltage feedback signal via the AMPOUT pin through the
internal VID DAC and is compared to the internal reference
voltage. When the load current increases, it causes a slight
decrease in the EAIN pin voltage relative to the 0.6V
reference, which in turn causes the ITH voltage to increase
until each inductor’s average current matches one third of
the new load current (assuming all three current sensing
resistors are equal). In Burst Mode operation and stage
shedding mode, after each top MOSFET has turned off, the
bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by current compara-
tor I2, or the beginning of the next cycle.
3730fa
9