LTC3730_15 Datasheet, PDF (23/28 Pages) Linear Technology – 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller

LTC3730
APPLICATIO S I FOR ATIO
7) Minimize trace impedances of TG, BG and SW nets. TG
and SW must be routed in parallel with minimum distance.
Figure 12 illustrates all branch currents in a three-phase
switching regulator. It becomes very clear after studying
the current waveforms why it is critical to keep the high
switching current paths to a small physical size. High elec-
tric and magnetic fields will radiate from these “loops” just
as radio stations transmit signals. The output capacitor
ground should return to the negative terminal of the input
capacitor and not share a common ground path with any
switched current paths. The left half of the circuit gives rise
to the “noise” generated by a switching regulator. The
ground terminations of the synchronous MOSFETs and
Schottky diodes should return to the bottom plate(s) of the
input capacitor(s) with a short isolated PC trace since very
high switched currents are present. A separate isolated path
from the bottom plate(s) of the input and output capacitor(s)
should be used to tie in the IC power ground pin (PGND).
This technique keeps inherent signals generated by high
current pulses taking alternate current paths that have fi-
nite impedances during the total period of the switching
regulator. External OPTI-LOOP compensation allows over-
compensation for PC layouts which are not optimized but
this is not the recommended design procedure.
SW1
D1
L1
R_SENSE1
V_IN
R_{IN +}
C_IN
SW2
D2
L2
R_SENSE2
V_OUT
+
C_OUT
R_L
BOLD LINES INDICATE HIGH
SWITCHING CURRENTS.
KEEP LINES TO A MININMUM
LENGTH.
SW3
D3
L3
R_SENSE3
Figure 12
3730 F12
3730fa
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