LTC3730_15 Datasheet, PDF (24/28 Pages) Linear Technology – 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller

LTC3730
APPLICATIO S I FOR ATIO
Simplified Visual Explanation of How a 3-Phase
Controller Reduces Both Input and Output RMS
Ripple Current
The effect of multiphase power supply design significantly
reduces the amount of ripple current in both the input and
output capacitors. The RMS input ripple current is divided
by, and the effective ripple frequency is multiplied up by
the number of phases used (assuming that the input
voltage is greater than the number of phases used times
the output voltage). The output ripple amplitude is also
reduced by, and the effective ripple frequency is increased
by the number of phases used. Figure 13 graphically
illustrates the principle.
SW V
SINGLE PHASE
I_CIN
I_COUT
SW1 V
SW2 V
SW3 V
I_L1
I_L2
I_L3
I_CIN
I_COUT
TRIPLE PHASE
Figure 13
3730 F13
The worst-case input RMS ripple current for a single stage
design peaks at twice the value of the output voltage. The
worst-case input RMS ripple current for a two stage
design results in peaks at 1/4 and 3/4 of the input voltage,
and the worst-case input RMS ripple current for a three
stage design results in peaks at 1/6, 1/2, and 5/6 of the
input voltage. The peaks, however, are at ever decreasing
levels with the addition of more phases. A higher effective
duty factor results because the duty factors “add” as long
as the currents in each stage are balanced. Refer to AN19
for a detailed description of how to calculate RMS current
for the single stage switching regulator.
Figure 6 illustrates the RMS input current drawn from the
input capacitance versus the duty cycle as determined by
the ration of input and output voltage. The peak input RMS
current level of the single phase system is reduced by 2/3
in a 3-phase solution due to the current splitting between
the three stages.
The output ripple current is reduced significantly when
compared to the single phase solution using the same
inductance value because the V_OUT/L discharge currents
term from the stages that has their bottom MOSFETs on
subtract current from the (V_CC – V_OUT)/L charging current
resulting from the stage which has its top MOSFET on. The
output ripple current for a 3-phase design is:
I_P-P
=
V_OUT
(^f)(^L)
(^1–
3DC₎
V_IN > 3V_OUT
The ripple frequency is also increased by three, further
reducing the required output capacitance when V_CC < 3V_OUT
as illustrated in Figure 6.
The addition of more phases, by phase locking additional
controllers, always results in no net input or output ripple
at V_OUT/V_IN ratios equal to the number of stages imple-
mented. Designing a system with multiple stages close to
the V_OUT/V_IN ratio will significantly reduce the ripple
voltage at the input and outputs and thereby improve
efficiency, physical size and heat generation of the overall
switching power supply. Refer to Application Note 77 for
more information on Polyphase circuits.
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