LTC3730_15 Datasheet, PDF (10/28 Pages) Linear Technology – 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller

LTC3730
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OPERATIO (Refer to Functional Diagram)
The top MOSFET drivers are biased from floating boot-
strap capacitor C_B, which is normally recharged through
an external Schottky diode during each off cycle. When V_IN
decreases to a voltage close to V_OUT, however, the loop
may enter dropout and attempt to turn on the top MOSFET
continuously. The dropout detector counts the number of
oscillator cycles that the bottom MOSFET remains off and
periodically forces a brief on period to allow C_B to re-
charge.
The main control loop is shut down by pulling the RUN/SS
pin low. Releasing RUN/SS allows an internal 1.5µA
current source to charge soft-start capacitor C_SS. When
C_SS reaches 1.5V, the main control loop is enabled and the
internally buffered I_TH voltage is clamped but allowed to
ramp as the voltage on C_SS continues to ramp. This “soft-
start” clamping prevents abrupt current from being drawn
from the input power source. When the RUN/SS pin is low,
all functions are kept in a controlled state. The RUN/SS pin
is pulled low when the V_CC input voltage is below 4V or
when the IC die temperature rises above 150°C.
Low Current Operation
The FCB pin is a multifunction pin: 1) an analog compara-
tor input to provide regulation for a secondary winding by
forcing temporary forced PWM operation and 2) a logic
input to select between three modes of operation.
A) Burst Mode Operation
When the FCB pin voltage is below 0.6V, the controller
performs as a continuous, PWM current mode synchro-
nous switching regulator. The top and bottom MOSFETs
are alternately turned on to maintain the output voltage
independent of direction of inductor current. When the
FCB pin is below V_CC – 1.5V but greater than 0.6V, the
controller performs as a Burst Mode switching regulator.
Burst Mode operation sets a minimum output current level
before turning off the top switch and turns off the synchro-
nous MOSFET(s) when the inductor current goes nega-
tive. This combination of requirements will, at low current,
force the I_TH pin below a voltage threshold that will
temporarily shut off both output MOSFETs until the output
voltage drops slightly. There is a burst comparator having
60mV of hysteresis tied to the I_TH pin. This hysteresis
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results in output signals to the MOSFETs that turn them on
for several cycles, followed by a variable “sleep” interval
depending upon the load current. The resultant output
voltage ripple is held to a very small value by having the
hysteretic comparator after the error amplifier gain block.
B) Stage Shedding Operation
When the FCB pin is tied to the V_CC pin, Burst Mode
operation is disabled and the forced minimum inductor
current requirement is removed. This provides constant
frequency, discontinuous current operation over the wid-
est possible output current range. At approximately 10%
of maximum designed load current, the second and third
output stages are shut off and the first output stage alone
is active in discontinuous current mode. This “stage
shedding” optimizes efficiency by eliminating the gate
charging losses and switching losses of the other two
output stages. Additional cycles will be skipped when the
output load current drops below 1% of maximum de-
signed load current in order to maintain the output voltage.
This Stage Shedding operation is not as efficient as Burst
Mode operation at very light loads, but does provide lower
noise, constant frequency operating mode down to light
load conditions.
C) Continuous Current Operation
Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When sinking current
while in forced continuous operation, the controller will
cause current to flow back into the input filter capacitor.
If large enough, this element will prevent the input supply
from boosting to unacceptably high levels; see C_OUT
selection in the Applications Information Section.
Frequency Synchronization
The phase-locked loop allows the internal oscillator to be
synchronized to an external source using the PLLIN pin.
The output of the phase detector at the PLLFLTR pin is also
the DC frequency control input of the oscillator, which
operates over a 250kHz to 600kHz range corresponding to
a voltage input from 0V to 2.4V. When locked, the PLL
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