LTC3730_15 Datasheet, PDF (20/28 Pages) Linear Technology – 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller

LTC3730
APPLICATIO S I FOR ATIO
The minimum on-time for the IC is generally about 110ns.
However, as the peak sense voltage decreases the mini-
mum on-time gradually increases. This is of particular
concern in forced continuous applications with low ripple
current at light loads. If the duty cycle drops below the
minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
If an application can operate close to the minimum on-
time limit, an inductor must be chosen that is low enough
in value to provide sufficient ripple amplitude to meet the
minimum on-time requirement. As a general rule, keep
the inductor ripple current for each channel equal to or
greater than 30% of I_OUT(MAX) at V_IN(MAX).
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, V_OUT shifts by an
amount equal to ∆I_LOAD • ESR, where ESR is the effective
series resistance of C_OUT. ∆I_LOAD also begins to charge or
discharge C_OUT, generating the feedback error signal that
forces the regulator to adapt to the current change and
return V_OUT to its steady-state value. During this recovery
time, V_OUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the I_TH pin not only allows optimization of
control loop behavior, but also provides a DC coupled
and AC filtered closed-loop response test point. The DC
step, rise time and settling at this test point truly reflects
the closed-loop response. Assuming a predominantly
20
second order system, phase margin and/or damping
factor can be estimated using the percentage of overshoot
seen at this pin. The bandwidth can also be estimated by
examining the rise time at the pin. The I_TH external com-
ponents shown in the Figure 1 circuit will provide an
adequate starting point for most applications.
The I_TH series R_C-C_C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to maximize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon because the various types and values determine the
loop feedback factor gain and phase. An output current
pulse of 20% to 80% of full load current having a rise time
of <2µs will produce output voltage and I_TH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop. The initial output voltage step,
resulting from the step change in output current, may not
be within the bandwidth of the feedback loop, so this signal
cannot be used to determine phase margin. This is why it
is better to look at the I_TH pin signal which is in the
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased by
increasing R_C and the bandwidth of the loop will be
increased by decreasing C_C. If R_C is increased by the same
factor that C_C is decreased, the zero frequency will be kept
the same, thereby keeping the phase the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual over-
all supply performance.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C_OUT, causing a rapid drop in V_OUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If C_LOAD is greater
than 2% of C_OUT , the switch rise time should be controlled
so that the load rise time is limited to approximately
1000 • R_SENSE • C_LOAD. Thus a 250µF capacitor and a 2mΩ
R_SENSE resistor would require a 500µs rise time, limiting
the charging current to about 1A.
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