LTC3730_15 Datasheet, PDF (14/28 Pages) Linear Technology – 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller

LTC3730
APPLICATIO S I FOR ATIO
drain-to-gate accumulation capacitance and the gate-to-
source capacitance. The Miller charge (the increase in
coulombs on the horizontal axis from a to b while the curve
is flat) is specified for a given V_DS drain voltage, but can be
adjusted for different V_DS voltages by multiplying by the
ratio of the application V_DS to the curve specified V_DS
values. A way to estimate the C_MILLER term is to take the
change in gate charge from points a and b on a manufac-
turers data sheet and divide by the stated V_DS voltage
specified. C_MILLER is the most important selection criteria
for determining the transition loss term in the top MOSFET
but is not directly specified on MOSFET data sheets. C_RSS
and C_OS are specified sometimes but definitions of these
parameters are not included.
MILLER EFFECT
V_GS
V
a
b
Q_IN
+
C_MILLER = (Q_B – Q_A)/V_DS
V_GS
–
Figure 5
V_IN
+
V_DS
–
3730 F05
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle = ^VOUT
V_IN
Synchronous
Switch Duty
Cycle
=
⎛
⎝⎜
V_IN
– V_OUT
V_IN
⎞
⎠⎟
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
( ) ^PMAIN
=
V_OUT
V_IN
⎛ _IMAX ⎞ ²
⎝⎜ N ⎠⎟
1+ δ
R_DS(ON)
+
( )( ) ^VIN2
I_MAX
2N
R_DR
C _MILLER
•
( ) ^⎡
⎢
1
+
1
⎤
⎥f
⎣⎢^{VCC – VTH(IL) VTH(IL)} ⎦⎥
( ) ^PSYNC
=
V_IN
– V_OUT
V_IN
⎛ _IMAX ⎞ ²
⎝⎜ N ⎠⎟
1+ δ
R_DS(ON)
14
where N is the number of output stages, δ is the tempera-
ture dependency of R_DS(ON), R_DR is the effective top driver
resistance (approximately 2Ω at V_GS = V_MILLER), V_IN is the
drain potential and the change in drain potential in the
particular application. V_TH(IL) is the data sheet specified
typical gate threshold voltage specified in the power
MOSFET data sheet at the specified drain current. C_MILLER
is the calculated capacitance using the gate charge curve
from the MOSFET data sheet and the technique described
above.
Both MOSFETs have I²R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V_IN < 12V, the
high current efficiency generally improves with larger
MOSFETs, while for V_IN > 12V, the transition losses
rapidly increase to the point that the use of a higher
R_DS(ON) device with lower C_MILLER actually provides higher
efficiency. The synchronous MOSFET losses are greatest
at high input voltage when the top switch duty factor is low
or during a short circuit when the synchronous switch is
on close to 100% of the period.
The term (1 + δ ) is generally given for a MOSFET in the
form of a normalized R_DS(ON) vs temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The Schottky diodes, (D1 to D3 in Figure 1) conduct during
the dead time between the conduction of the two large
power MOSFETs. This prevents the body diode of the
bottom MOSFET from turning on, storing charge during
the dead time and requiring a reverse recovery period
which could cost as much as several percent in efficiency.
A 2A to 8A Schottky is generally a good compromise for
both regions of operation due to the relatively small
average current. Larger diodes result in additional transi-
tion loss due to their larger junction capacitance.
C_IN and C_OUT Selection
In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V_OUT/V_IN.
A low ESR input capacitor sized for the maximum RMS
current must be used. The details of a close form equation
can be found in Application Note 77. Figure 6 shows the
input capacitor ripple current for different phase configu-
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