LTC3730_15 Datasheet, PDF (15/28 Pages) Linear Technology – 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller

LTC3730
APPLICATIO S I FOR ATIO
rations with the output voltage fixed and input voltage
varied. The input ripple current is normalized against the
DC output current. The graph can be used in place of
tedious calculations. The minimum input ripple current
can be achieved when the product of phase number and
output voltage, N(V_OUT), is approximately equal to the
input voltage V_IN or:
V_{OUT =} k _{where k = 1, 2, ..., N – 1}
V_IN N
So the phase number can be chosen to minimize the input
capacitor size for the given input and output voltages.
In the graph of Figure 4, the local maximum input RMS
capacitor currents are reached when:
V_{OUT =} 2k – 1 _{where k = 1, 2, ..., N}
V_IN
N
These worst-case conditions are commonly used for de-
sign because even significant deviations do not offer much
relief. Note that capacitor manufacturer’s ripple current
ratings are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than re-
quired. Several capacitors may also be paralleled to meet
size or height requirements in the design. Always consult
the capacitor manufacturer if there is any question.
The Figure 6 graph shows that the peak RMS input current
is reduced linearly, inversely proportional to the number N
0.6
0.5
1-PHASE
0.4
2-PHASE
3-PHASE
0.3
4-PHASE
6-PHASE
0.2
0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
DUTY FACTOR (V_OUT/V_IN)
3730 F06
Figure 6. Normalized Input RMS Ripple Current
vs Duty Factor for One to Six Output Stages
of stages used. It is important to note that the efficiency
loss is proportional to the input RMS current squared and
therefore a 3-stage implementation results in 90% less
power loss when compared to a single phase design.
Battery/input protection fuse resistance (if used), PC
board trace and connector resistance losses are also
reduced by the reduction of the input ripple current in a
PolyPhase system. The required amount of input capaci-
tance is further reduced by the factor, N, due to the
effective increase in the frequency of the current pulses.
Ceramic capacitors are becoming very popular for small
designs but several cautions should be observed. “X7R”,
“X5R” and “Y5V” are examples of a few of the ceramic
materials used as the dielectric layer, and these different
dielectrics have very different effect on the capacitance
value due to the voltage and temperature conditions
applied. Physically, if the capacitance value changes due
to applied voltage change, there is a concommitant piezo
effect which results in radiating sound! A load that draws
varying current at an audible rate may cause an attendant
varying input voltage on a ceramic capacitor, resulting in
an audible signal. A secondary issue relates to the energy
flowing back into a ceramic capacitor whose capacitance
value is being reduced by the increasing charge. The
voltage can increase at a considerably higher rate than the
constant current being supplied because the capacitance
value is decreasing as the voltage is increasing! Neverthe-
less, ceramic capacitors, when properly selected and
used, can provide the lowest overall loss due to their
extremely low ESR.
The selection of C_OUT is driven by the required effective
series resistance (ESR). Typically once the ESR require-
ment is satisfied the capacitance is adequate for filtering.
The steady-state output ripple (∆V_OUT) is determined by:
∆V_OUT
≈
∆I_RIPPLE^{⎛⎝⎜} ESR
+
1
8NfC _OUT
⎞
⎠⎟
where f = operating frequency of each stage, N is the
number of output stages, C_OUT = output capacitance and
∆I_L = ripple current in each inductor. The output ripple is
highest at maximum input voltage since ∆I_L increases
with input voltage. The output ripple will be less than 50mV
at max V_IN with ∆I_L = 0.4I_OUT(MAX) assuming:
3730fa
15