LTC3730_15 Datasheet, PDF (22/28 Pages) Linear Technology – 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller

LTC3730
APPLICATIO S I FOR ATIO
The worst-case power dissipation by the synchronous
MOSFET under normal operating conditions at elevated
ambient temperature and estimated 50°C junction tem-
perature rise is:
P_SYNC
=
20V − 1.3V
20V
(^15A)² (^1.25)(^0.007Ω)
=
1.84W
A short circuit to ground will result in a folded back current
of:
( ) ^{( ) ISC ≈}
25mV
2 + 3 mΩ
+
21 ^{⎛⎝⎜⎜}
150ns 20V
0.6µH
⎞
⎠⎟⎟
=
7.5A
with a typical value of R_DS(ON) and d = (0.005/°C)(50°C) =
0.25. The resulting power dissipated in the bottom MOSFET
is:
P_SYNC = (7.5A)²(1.25)(0.007Ω) ≈ 0.5W
which is less than one third of the normal, full load
conditions. Incidentally, since the load no longer dissi-
pates any power, total system power is decreased by over
90%. Therefore, the system actually cools significantly
during a shorted condition!
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
IC. These items are also illustrated graphically in the layout
diagram of Figure 12. Check the following in the PC layout:
1) Are the signal and power ground paths isolated? Keep the
SGND at one end of a printed circuit path thus preventing
MOSFET currents from traveling under the IC. The IC signal
ground pin should be used to hook up all control circuitry
on one side of the IC, routing the copper through SGND,
under the IC covering the “shadow” of the package, connect-
ing to the PGND pin and then continuing on to the (–) plates
of C_IN and C_OUT. The V_CC decoupling capacitor should be
placed immediately adjacent to the IC between the V_CC pin
and PGND. A 1µF ceramic capacitor of the X7R or X5R type
is small enough to fit very close to the IC to minimize the ill
effects of the large current pulses drawn to drive the bottom
MOSFETs. An additional 4.7µF to 10µF of ceramic, tantalum
or other very low ESR capacitance is recommended in or-
22
der to keep the internal IC supply quiet. The power ground
returns to the sources of the bottom N-channel MOSFETs,
anodes of the Schottky diodes and (–) plates of C_IN, which
should have as short lead lengths as possible.
2) Does the IC IN⁺ pin connect to the (+) plates of C_OUT?
A 30pF to 300pF feedforward capacitor between the
AMPOUT and EAIN pins should be placed as close as
possible to the IC.
3) Are the SENSE^– and SENSE⁺ printed circuit traces for
each channel routed together with minimum PC trace
spacing? The filter capacitors between SENSE⁺ and SENSE^–
for each channel should be as close as possible to the pins
of the IC. Connect the SENSE^– and SENSE⁺ pins to the
pads of the sense resistor as illustrated in Figure 11.
INDUCTOR
LTC3730
SENSE⁺
SENSE^–
1000pF
SENSE
RESISTOR
3730 F11
OUTPUT CAPACITOR
Figure 11. Kelvin Sensing R_SENSE
4) Do the (+) plates of C_IN connect to the drains of the
topside MOSFETs as closely as possible? This capacitor
provides the pulsed current to the MOSFETs. (The loop
area formed by C_IN, topside MOSFET and bottom MOSFETs
must be minimized.)
5) Keep the switching nodes, SWITCH, BOOST and TG
away from sensitive small-signal nodes (SENSE⁺,
SENSE^–, IN⁺, IN ^–, EAIN). Ideally the SWITCH, BOOST and
TG printed circuit traces should be routed away and
separated from the IC and the “quiet” side of the IC.
Separate the high dV/dt printed circuit traces from sensi-
tive small-signal nodes with ground traces or ground
planes.
6) Use a low impedance source such as a logic gate to drive
the PLLIN pin and keep the lead as short as possible.
3730fa