LTC3730_15 Datasheet, PDF (17/28 Pages) Linear Technology – 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller

LTC3730
APPLICATIO S I FOR ATIO
30 to 100 times that of the total gate charge capacitance of
the topside MOSFET(s) as specified on the manufacturer’s
data sheet. The reverse breakdown of D_B must be greater
than V_IN(MAX).
Operational Amplifier
The amplifier has a 0 to V_CC – 1.4V common mode input
range and an output swing range of 0 to V_CC – 1.2V. The
output uses an NPN emitter follower without any internal
pull-down current. A DC resistive load to ground is re-
quired in order to sink current.
Output Voltage
The IC includes a digitally controlled 5-bit attenuator
between the AMPOUT pin and the EAIN pin resulting in
output voltages as defined in Table 1. Output voltages with
25mV increments are produced from 0.6V to 1V and 50mV
increments from 1V to 1.75V.
Each VID digital input is pulled up to a logical high with an
internal 3µA. The input logic threshold is approximately
1.2V but the input circuit can withstand an input voltage of
up to 7V.
Table 1. VID Output Voltage Programming
CODE
V_OUT
CODE
V_OUT
B4 B3 B2 B1 B0
B4 B3 B2 B1 B0
1 1 1 1 1 0.600V 0 1 1 1 1 1.000V
1 1 1 1 0 0.625V 0 1 1 1 0 1.050V
1 1 1 0 1 0.650V 0 1 1 0 1 1.100V
1 1 1 0 0 0.675V 0 1 1 0 0 1.150V
1 1 0 1 1 0.700V 0 1 0 1 1 1.200V
1 1 0 1 0 0.725V 0 1 0 1 0 1.250V
1 1 0 0 1 0.750V 0 1 0 0 1 1.300V
1 1 0 0 0 0.775V 0 1 0 0 0 1.350V
1 0 1 1 1 0.800V 0 0 1 1 1 1.400V
1 0 1 1 0 0.825V 0 0 1 1 0 1.450V
1 0 1 0 1 0.850V 0 0 1 0 1 1.500V
1 0 1 0 0 0.875V 0 0 1 0 0 1.550V
1 0 0 1 1 0.900V 0 0 0 1 1 1.600V
1 0 0 1 0 0.925V 0 0 0 1 0 1.650V
1 0 0 0 1 0.950V 0 0 0 0 1 1.700V
1 0 0 0 0 0.975V 0 0 0 0 0 1.750V
Soft-Start/Run Function
The RUN/SS pin provides three functions: 1) ON/OFF, 2)
soft-start and 3) a defeatable short-circuit latch off timer.
Soft-start reduces the input power sources’ surge cur-
rents by gradually increasing the controller’s current limit
(proportional to an internal buffered and clamped V_ITH).
The latchoff timer prevents very short, extreme load
transients from tripping the overcurrent latch. A small
pull-up current (>5µA) supplied to the RUN/SS pin will
prevent the overcurrent latch from operating. A maximum
pull-up current of 200µA is allowed into the RUN/SS pin
even though the voltage at the pin may exceed the absolute
maximum rating for the pin. This is a result of the limited
current and the internal protection circuit on the pin. The
following explanation describes how this function oper-
ates.
An internal 1.5µA current source charges up the C_SS
capacitor. When the voltage on RUN/SS reaches 1.5V, the
controller is permitted to start operating. As the voltage on
RUN/SS increases from 1.5V to 3V, the internal current
limit is increased from 0V/R_SENSE to 75mV/R_SENSE. The
output current limit ramps up slowly, taking an additional
1s/µF to reach full current. The output current thus ramps
up slowly, eliminating the starting surge current required
from the input power supply. If RUN/SS has been pulled all
the way to ground, there is a delay before starting of
approximately:
( ) ^t_DELAY
=
1.5V
1.5µA
C _SS
=
1s/µF
C _SS
( ) ^t_IRAMP
=
3V − 1.5V
1.5µA
C _SS
=
1s/µF
C _SS
By pulling the RUN/SS controller pin below 0.4V the IC is
put into low current shutdown (I_Q < 50µA). The RUN/SS
pin can be driven directly from logic as shown in Figure 7.
Diode D1 reduces the start delay but allows C_SS to ramp up
slowly, providing the soft-start function. The RUN/SS
pin has an internal 6V zener clamp (see the Functional
Diagram).
3730fa
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