LTC3730_15 Datasheet, PDF (18/28 Pages) Linear Technology – 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller

LTC3730
APPLICATIO S I FOR ATIO
Fault Conditions: Overcurrent Latchoff
The RUN/SS pins also provide the ability to latch off the
controllers when an overcurrent condition is detected. The
RUN/SS capacitor is used initially to turn on and limit the
inrush current of all three output stages. After the control-
lers have been started and been given adequate time to
charge up the output capacitor and provide full load
current, the RUN/SS capacitor is used for a short-circuit
timer. If the output voltage falls to less than 70% of its
nominal value, the RUN/SS capacitor begins discharging
on the assumption that the output is in an overcurrent
condition. If the condition lasts for a long enough period,
as determined by the size of the RUN/SS capacitor, the
discharge current, and the circuit trip point, the controller
will be shut down until the RUN/SS pin voltage is recycled.
If the overload occurs during start-up, the time can be
approximated by:
t_LO1 >> (C_SS • 0.6V)/(1.5µA) = 4 • 10⁵ (C_SS)
If the overload occurs after start-up, the voltage on the
RUN/SS capacitor will continue charging and will provide
additional time before latching off:
t_LO2 >> (C_SS • 3V)/(1.5µA) = 2 • 10⁶ (C_SS)
This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor to the RUN/SS pin from V_CC
as shown in Figure 7. When V_CC is 5V, a 200k resistance
will prevent the discharge of the RUN/SS capacitor
during an overcurrent condition but also shortens the
soft-start period, so a larger RUN/SS capacitor value may
be required.
3.3V OR 5V
RUN/SS PIN
V_{CC RUN/SS PIN}
5V
D1
R_SS
SHDN
SHDN
C_SS
C_SS
3730 F07
Figure 7. RUN/SS Pin Interfacing
Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem with
noise pick-up or poor layout causing the protection circuit
to latch off the controller. Defeating this feature allows
troubleshooting of the circuit and PC layout. The internal
foldback current limiting still remains active, thereby
18
protecting the power supply system from failure. A deci-
sion can be made after the design is complete whether to
rely solely on foldback current limiting or to enable the
latchoff feature by removing the pull-up resistor.
The value of the soft-start capacitor C_SS may need to be
scaled with output current, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:
C_SS > (C_OUT )(V_OUT) (10^–4) (R_SENSE)
The minimum recommended soft-start capacitor of
C_SS = 0.1µF will be sufficient for most applications.
Current Foldback
In certain applications, it may be desirable to defeat the
internal current foldback function. A negative impedance
is experienced when powering a switching regulator.
That is, the input current is higher at a lower V_IN and
decreases as V_IN is increased. Current foldback is de-
signed to accommodate a normal, resistive load having
increasing current draw with increasing voltage. The EAIN
pin should be artificially held 70% above its nominal
operating level of 0.6V, or 0.42V in order to prevent the IC
from “folding back” the peak current level. A suggested
circuit is shown in Figure 8.
V_CC
V_CC
CALCULATE FOR
0.42V TO 0.55V
LTC3730
Q1
EAIN
3730 F08
Figure 8. Foldback Current Elimination
The emitter of Q1 will hold up the EAIN pin to a voltage in
the absence of V_OUT that will prevent the internal sensing
circuitry from reducing the peak output current. Remov-
ing the function in this manner eliminates the external
MOSFET’s protective feature under short-circuit condi-
tions. This technique will also prevent the short-circuit
latchoff function from turning off the part during a short-
circuit event and the peak output current will only be
limited to N • 75mV/R_SENSE.
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