LTC3730_15 Datasheet, PDF (11/28 Pages) Linear Technology – 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller

U
OPERATIO (Refer to Functional Diagram)
aligns the turn on of the top MOSFET to the rising edge of
the synchronizing signal. When no frequency information
is supplied to the PLLIN pin, PLLFLTR goes low, forcing
the oscillator to minimum frequency. A DC source can be
applied to the PLLFLTR pin to externally set the desired
operating frequency. A discharge current of approxi-
mately 20µA will be present at the pin with no PLLIN
signal.
Input capacitance ESR requirements and efficiency losses
are reduced substantially in a multiphase architecture
because the peak current drawn from the input capacitor
is effectively divided by the number of phases used and
power loss is proportional to the RMS current squared. A
3-stage, single output voltage implementation can reduce
input path power loss by 90%.
Operational Amplifier
This amplifier can be used to satisfy output voltage re-
quirements that change according to the mode of circuit or
CPU operation. The output voltage can be dropped several
hundred millivolts when using an externally switched
resistive divider based upon the activity level or speed
requirement by changing the output voltage feedback
factor. The amplifier can swing to within 1.2V of the
positive power supply at low output current (≤1mA). The
amplifier has an output slew rate of 5V/µs and is capable
of driving capacitive loads at an output sourcing RMS
current of up to 10mA.
Power Good
The PGOOD pin is connected to the drain of an internal
N-channel MOSFET. The MOSFET is turned on once an
internal delay has elapsed and the output voltage has been
away from its nominal value by greater than 10%. If the
output returns to normal prior to the delay timeout, the
timer is reset. There is no delay time for the rising of the
PGOOD output once the output voltage is within the ±10%
“window.”
LTC3730
Short-Circuit Detection
The RUN/SS capacitor is used initially to turn on and limit
the inrush current from the input power source. Once the
controllers have been given time, as determined by the
capacitor on the RUN/SS pin, to charge up the output
capacitors and provide full load current, the RUN/SS
capacitor is then used as a short-circuit timeout circuit. If
the output voltage falls to less than 70% of its nominal
output voltage, the RUN/SS capacitor begins discharging,
assuming that the output is in a severe overcurrent and/or
short-circuit condition. If the condition lasts for a long
enough period, as determined by the size of the RUN/SS
capacitor, the controller will be shut down until the RUN/SS
pin voltage is recycled. This built-in latchoff can be over-
ridden by providing >5µA at a compliance of 3.8V to the
RUN/SS pin. This additional current shortens the soft-
start period but prevents net discharge of the RUN/SS
capacitor during a severe overcurrent and/or short-circuit
condition. Foldback current limiting is activated when the
output voltage falls below 70% of its nominal level whether
or not the short-circuit latchoff circuit is enabled. Foldback
current limit can be overridden by clamping the EAIN pin
such that the voltage is held above the (70%)(0.6V) or
0.42V level even when the actual output voltage is low.
Input Undervoltage Reset
The RUN/SS capacitor will be reset if the input voltage
(V_CC) is allowed to fall below approximately 3.8V. The
capacitor on the pin will be discharged until the short-
circuit arming latch is disarmed. The RUN/SS capacitor
will attempt to cycle through a normal soft-start ramp up
after the V_CC supply rises above 3.8V. This circuit prevents
power supply latchoff in the event of input power switch-
ing break-before-make situations. The PGOOD pin is held
low during start-up until the RUN/SS capacitor rises above
the short-circuit latchoff arming threshold of approxi-
mately 3.8V.
3730fa
11