LTC3730_15 Datasheet, PDF (13/28 Pages) Linear Technology – 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller

LTC3730
APPLICATIO S I FOR ATIO
Accepting larger values of ∆I_L allows the use of low
inductances but can result in higher output voltage ripple.
A reasonable starting point for setting ripple current is
∆I_L = 0.4(I_OUT)/N, where N is the number of channels and
I_OUT is the total load current. Remember, the maximum
∆I_L occurs at the maximum input voltage. The individual
inductor ripple currents are constant determined by the
input and output voltages and the inductance.
1.0
1-PHASE
0.9
2-PHASE
0.8
3-PHASE
4-PHASE
0.7
6-PHASE
0.6
0.5
0.4
0.3
0.2
0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
DUTY FACTOR (V_OUT/V_IN)
3730 F04
Figure 4. Normalized Peak Output Current
vs Duty Factor [I_RMS = 0.3(I_O(P-P))]
Inductor Core Selection
Once the value for L1 to L3 is known, the type of inductor
must be selected. High efficiency converters generally
cannot afford the core loss found in low cost powdered
iron cores, forcing the use of ferrite, molypermalloy or
Kool Mµ^® cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will
increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design
current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu-
facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire. Be-
cause they lack a bobbin, mounting is more difficult.
However, designs for surface mount are available which
do not increase the height significantly.
Power MOSFET and D1, D2, D3 Selection
At least two external power MOSFETs must be selected for
each of the three output sections: One N-channel MOSFET
for the top (main) switch and one or more N-channel
MOSFET(s) for the bottom (synchronous) switch. The
number, type and “on” resistance of all MOSFETs selected
take into account the voltage step-down ratio as well as the
actual position (main or synchronous) in which the MOSFET
will be used. A much smaller and much lower input
capacitance MOSFET should be used for the top MOSFET
in applications that have an output voltage that is less than
1/3 of the input voltage. In applications where V_IN >> V_OUT,
the top MOSFETs’ “on” resistance is normally less impor-
tant for overall efficiency than its input capacitance at
operating frequencies above 300kHz. MOSFET manufac-
turers have designed special purpose devices that provide
reasonably low “on” resistance with significantly reduced
input capacitance for the main switch application in switch-
ing regulators.
The peak-to-peak MOSFET gate drive levels are set by the
voltage, V_CC, requiring the use of logic-level threshold
MOSFETs in most applications. Pay close attention to the
BV_DSS specification for the MOSFETs as well; many of the
logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “on”
resistance R_DS(ON), input capacitance, input voltage and
maximum output current.
MOSFET input capacitance is a combination of several
components but can be taken from the typical “gate
charge” curve included on most data sheets. The curve is
generated by forcing a constant input current into the gate
of a common source, current source loaded stage and
then plotting the gate voltage versus time. The initial slope
is the effect of the gate-to-source and the gate-to-drain
capacitance. The flat portion of the curve is the result
of the Miller multiplication effect of the drain-to-gate
capacitance as the drain drops the voltage across the
current source load. The upper sloping line is due to the
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