LTC3730_15 Datasheet, PDF (8/28 Pages) Linear Technology – 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller

LTC3730
PI FU CTIO S
VID0 to VID4 (Pins 1, 18, 19, 20, 36): Output Voltage
Programming Input Pins. A 3µA internal pull-up current is
provided on each input pin. See Table 1 for details. Do not
apply voltage to these pins prior to the application of
voltage on the V_CC pin.
PLLIN (Pin 2): Synchronization Input to Phase Detector.
This pin is internally terminated to SGND with 50kΩ. The
phase-locked loop will force the rising top gate signal of
controller 1 to be synchronized with the rising edge of the
PLLIN signal.
PLLFLTR (Pin 3): The phase-locked loop’s lowpass filter
is tied to this pin. Alternatively, this pin can be driven with
an AC or DC voltage source to vary the frequency of the
internal oscillator. (Do not apply voltage to this pin prior to
the application of voltage on the V_CC pin.)
FCB (Pin 4): Forced Continuous Control Input. The voltage
applied to this pin sets the operating mode of the control-
ler. The forced continuous current mode is active when the
applied voltage is less than 0.6V. Burst Mode operation
will be active when the pin is allowed to float and a stage
shedding mode will be active if the pin is tied to the V_CC pin.
(Do not apply voltage to this pin prior to the application of
voltage on the V_CC pin.)
IN⁺, IN^– (Pins 5, 6): Inputs to an Operational Amplifier.
AMPOUT (Pin 7): Output of the Operational Amplifier. This
amplifier can be used as a switchable voltage gain ampli-
fier to determine the output voltage or as a remote sensing
amplifier.
EAIN (Pin 8): This is the input to the error amplifier which
compares the internally VID divided output voltage to the
internal 0.6V reference voltage.
SGND (Pin 9): Signal Ground. This pin must be routed
separately under the IC to the PGND pin and then to the
main ground plane.
SENSE1⁺, SENSE2⁺, SENSE3⁺, SENSE1^–, SENSE2^–,
SENSE3^– (Pins 10 to 15): The Inputs to Each Differential
Current Comparator. The I_TH pin voltage and built-in
offsets between SENSE^– and SENSE⁺ pins, in conjunction
with R_SENSE, set the current trip threshold level.
RUN/SS (Pin 16): Combination of Soft-Start, Run Con-
trol Input and Short-Circuit Detection Timer. A capacitor
to ground at this pin sets the ramp time to full current
output as well as the time delay prior to an output voltage
short-circuit shutdown. A minimum value of 0.01µF is
recommended on this pin.
I_TH (Pin 17): Error Amplifier Output and Switching Regu-
lator Compensation Point. All three current comparators’
thresholds increase with this control voltage.
PGND (Pin 26): Driver Power Ground. This pin connects
to the sources of the bottom N-channel external MOSFETs
and the (–) terminals of C_IN.
BG1 to BG3 (Pins 27, 25, 24): High Current Gate Drives for
Bottom N-Channel MOSFETs. Voltage swing at these pins
is from ground to V_CC.
V_CC (Pin 28): Main Supply Pin. Because this pin supplies
both the controller circuit power as well as the high power
pulses supplied to drive the external MOSFET gates, this
pin needs to be very carefully and closely decoupled to the
IC’s PGND pin.
SW1 to SW3 (Pins 32, 29, 23): Switch Node Connections
to Inductors. Voltage swing at these pins is from a Schot-
tky diode (external) voltage drop below ground to V_IN
(where V_IN is the external MOSFET supply rail).
TG1 to TG3 (Pins 33, 30, 22): High Current Gate Drives for
Top N-channel MOSFETs. These are the outputs of floating
drivers with a voltage swing equal to the boost voltage
source superimposed on the switch node voltage SW.
BOOST1 to BOOST3 (Pins 34, 31, 21): Positive Supply
Pins to the Topside Floating Drivers. Bootstrapped capaci-
tors, charged with external Schottky diodes and a boost
voltage source, are connected between the BOOST and
SW pins. Voltage swing at the BOOST pins is from boost
source voltage (typically V_CC) to this boost source voltage
+V_IN (where V_IN is the external MOSFET supply rail).
PGOOD (Pin 35): This open-drain output is pulled low when
the output voltage has been outside the PGOOD tolerance
window for the V_UVDLY delay of approximately 100µs.
3730fa
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