LTC3876_15 Datasheet, PDF (42/48 Pages) Linear Technology – Dual DC/DC Controller for DDR Power with Differential VDDQ Sensing and 50mA VTT Reference

LTC3876
APPLICATIONS INFORMATION
• Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. Connect the copper areas to DC rails only,
e.g., PGND.
PCB Layout Debugging
Only after each controller is checked for its individual
performance should both controllers be turned on at
the same time. It is helpful to use a DC-50MHz current
probe to monitor the current in the inductor while testing
the circuit. Monitor the output switching node (SW pin)
to synchronize the oscilloscope to the internal oscillator
output CLKOUT, or external clock if used. Probe the actual
output voltage as well. Check for proper performance over
the operating voltage and current range expected in the
application.
The frequency of operation should be maintained over
the input voltage range. The phase should be maintained
from cycle to cycle in a well designed, low noise PCB
implementation. Variation in the phase of SW node pulse
can suggest noise pickup at the current or voltage sensing
inputs or inadequate loop compensation. Overcompensa-
tion of the loop can be used to tame a poor PCB layout if
regulator bandwidth optimization is not required.
A particularly difficult region of operation is when one
controller channel is turning on (right after its current
comparator trip point) while the other channel is turning
off its top MOSFET at the end of its on-time. This may
cause minor phase-lock jitter at either channel due to
noise coupling.
Reduce V_IN from its nominal level to verify operation of
the regulator in dropout. Check the operation of the un-
dervoltage lockout circuit by further lowering V_IN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins.
The capacitor placed across the current sensing pins needs
to be placed immediately adjacent to the pins of the IC.
This capacitor helps to minimize the effects of differential
noise injection due to high frequency capacitive coupling.
If problems are encountered with high current output
loading at lower input voltages, look for inductive coupling
between C_IN, top and bottom MOSFET components to the
sensitive current and voltage sensing traces.
In addition, investigate common ground path voltage pickup
between these components and the SGND pin of the IC.
High Switching Frequency Operation
At high switching frequencies there may be an increased
sensitivity to noise. Special care may need to be taken to
prevent cycle-by-cycle instability and/or phase-lock jitter.
First, carefully follow the recommended layout techniques
to reduce coupling from the high switching voltage/current
traces. Additionally, use low ESR and low impedance X5R
or X7R ceramic input capacitors: up to 5μF per Amp. of
load current may be needed. If necessary, increase ripple
sense voltage by increasing sense resistance value and
V_RNG setting, to improve noise immunity.
3876f
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