LTC3876_15 Datasheet, PDF (24/48 Pages) Linear Technology – Dual DC/DC Controller for DDR Power with Differential VDDQ Sensing and 50mA VTT Reference

LTC3876
APPLICATIONS INFORMATION
The MOSFET power dissipations at maximum output a single-phase application. The maximum RMS capacitor
current are given by:
current is given by:
( ) P_TOP = D_TOP •I_OUT(MAX)2 •R_DS(ON)(MAX) 1+ δ + V_IN2
•
⎛
⎝⎜
I_{OUT(MAX )}
2
⎞
⎠⎟
• C_MILLER
⎡
R_TG(HI)
⎢
⎣
V_DRVCC
–
V_MILLER
+
R_TG(LO)
V_MILLER
⎤
⎥^•
⎦
f
I_RMS
≅ I_OUT(MAX)
•
V_OUT
V_IN
•
V_{IN – 1}
V_OUT
This formula has a maximum at V_IN = 2V_OUT, where
P_BOT = D_BOT • I_OUT(MAX)2 • R_DS(ON)(MAX) • (1 + δ )
I_RMS = I_OUT(MAX)/2. This simple worst-case condition
is commonly used for design because even significant
where δ is the temperature dependency of R_DS(ON), R_{TG(HI) deviations do not offer much relief. Note that capacitor}
is the TG pull-up resistance, and R_TG(LO) is the TG pull- _{manufacturers’ ripple current ratings are often based on}
down resistance. V_MILLER is the Miller effect V_GS voltage _{only 2000 hours of life. This makes it advisable to further}
and is taken graphically from the MOSFET’s data sheet. _{derate the capacitor or to choose a capacitor rated at a}
Both MOSFETs have I²R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For V_IN < 20V,
the high current efficiency generally improves with larger
MOSFETs, while for V_IN > 20V, the transition losses rapidly
increase to the point that the use of a higher R_DS(ON) device
with lower C_MILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
short-circuit when the synchronous switch is on close to
100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R_DS(ON) vs temperature curve in the
power MOSFET data sheet. For low voltage MOSFETs,
0.5% per degree (°C) can be used to estimate δ as an
approximation of percentage change of R_DS(ON):
δ = 0.005/°C • (T_J – T_A)
higher temperature than required. Several capacitors may
also be paralleled to meet size or height requirements in
the design. Due to the high operating frequency of the
LTC3876, additional ceramic capacitors should also be
used in parallel for C_IN close to the IC and power switches
to bypass the high frequency switching noises. Typically
multiple X5R or X7R ceramic capacitors are put in parallel
with either conductive-polymer or aluminum-electrolytic
types of bulk capacitors. Because of its low ESR, the ce-
ramic capacitors will take most of the RMS ripple current.
Vendors do not consistently specify the ripple current
rating for ceramics, but ceramics could also fail due to
excessive ripple current. Always consult the manufacturer
if there is any question.
Figure 6 represents a simplified circuit model for calculat-
ing the ripple currents in each of these capacitors. The
input inductance (L_IN) between the input source and the
input of the converter will affect the ripple current through
where T_J is estimated junction temperature of the MOSFET
L_IN
and T_A is ambient temperature.
1μH
C_IN Selection
In continuous mode, the source current of the top
N-channel MOSFET is a square wave of duty cycle V_OUT/
V_IN. To prevent large voltage transients, a low ESR input
capacitor sized for the maximum RMS current must be
used. The worst-case RMS current occurs by assuming
ESR_(BULK)
+– _VIN
ESL_(BULK)
+
C_IN(BULK)
ESR_(CERAMIC)
ESL_(CERAMIC)
C_IN(CERAMIC)
I_{PULSE(PHASE1)}
I_{PULSE(PHASE2)}
3876 F06
Figure 6. Circuit Model for Input Capacitor
Ripple Current Simulation
3876f
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