 English |
|
|
|
|
|
|
|
| LTC3876_15 Datasheet, PDF (41/48 Pages) Linear Technology – Dual DC/DC Controller for DDR Power with Differential VDDQ Sensing and 50mA VTT Reference | |||
| |||
| ◁ |
APPLICATIONS INFORMATION
LTC3876
SENSE2â
SENSE2+
VTTSNS
CITH1(2)
RITH1(2)
CITH2(2)
ITH2
LTC3876
LOCALIZED
SGND TRACE
RT
CITH2(1)
VRNG2
PHASMD
MODE/PLLIN
CLKOUT
SGND
RT
VRNG1
RITH1(1)
RITH2(1)
ITH1
CITH1(1)
TRACK/SS1
RFB2(1)
CSS1
RFB1(1)
VOUTSENSE1+
VOUTSENSE1â
SENSE1+
SENSE1â
PGOOD2
BOOST2
TG2
SW2
BG2
DRVCC2
EXTVCC
INTVCC
CVCC
PGND
VIN
DRVCC1
BG1
SW1
TG1
BOOST1
PGOOD1
RUN1
DTR1
CB2
DB2
RINTVCC
CINTVCC
CDRVCC
DB1
CB1
L2
RSENSE2
MT2
MB2
CERAMIC
COUT2
VOUT2
CVIN VIN
RVIN
+
CIN
CERAMIC
COUT1
MT1
MB1
RSENSE1
L1
GND
VOUT1
3876 F12
Figure 12. Recommended PCB Layout Diagram
⢠Place the resistor feedback divider RFB1, RFB2 close to
VOUTSENSE1+ and VOUTSENSE1â pins for channel 1, or
VFB2 pin for channel 2, so that the feedback voltage
tapped from the resistor divider will not be disturbed by
noise sources. Route remote sense PCB traces (use a
pair of wires closely together for differential sensing in
channel 1) directly to the terminals of output capacitors
for best output regulation.
⢠Place decoupling capacitors CITH2 next to the ITH and
SGND pins with short, direct trace connections.
⢠Use sufficient isolation when routing a clock signal into
the MODE/PLLIN pin or out of the CLKOUT pin, so that
the clock does not couple into sensitive pins.
⢠Place the ceramic decoupling capacitor CINTVCC between
the INTVCC pin and SGND and as close as possible to
the IC.
⢠Place the ceramic decoupling capacitor CDRVCC close
to the IC, between the combined DRVCC1,2 pins and
PGND.
⢠Filter the VIN input to the LTC3876 with an RC filter.
Place the filter capacitor close to the VIN pin.
⢠If vias have to be used, use immediate vias to connect
components to the SGND and PGND planes of LTC3876.
Use multiple large vias for power components.
3876f
41
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese