LTC3876_15 Datasheet, PDF (3/48 Pages) Linear Technology – Dual DC/DC Controller for DDR Power with Differential VDDQ Sensing and 50mA VTT Reference

LTC3876
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at T_A = 25°C. V_IN = 15V unless otherwise noted. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
Main Control Loop
V_IN
Input Voltage Operating Range
4.5
VDDQ(REG) VDDQ Regulated Operating Range
VDDQ Regulates Differentially with Respect
1.0
VTTR(REG)
VTTR Regulated Operating Range
to V_{OUTSENSE1–}, VTTSNS and VTTR Regulate
0.5
VTTSNS(REG) VTTSNS Regulated Operating Range
Differentially to One-Half VDDQ with Respect to
0.5
V_{OUSTSENSE1–}
38
V
2.5
V
1.25
V
1.25
V
I_Q
Input DC Supply Current
Both Channels Enabled
Shutdown Supply Current
MODE/PLLIN = 0V, No Load
RUN1 = RUN2 = 0V
5000
μA
20
μA
V_DFB1(REG)
Regulated Differential Feedback Voltage on ITH1 = 1.2V (Note 5)
Channel 1, VDDQ
(V_OUTSENSE1+ – V_{OUTSENSE1–})
T_A = 25°C
T_A = 0°C to 85°C
T_A = –40°C to 125°C
0.5985
0.6015
V
l 0.596 0.6 0.604
V
l 0.594 0.6 0.606
V
Regulated Differential Feedback Voltage
on Channel 1, VDDQ Over Line, Load and
Common Mode
V_IN = 4.5V to 38V, ITH1 = 0.5V to 1.9V,
V_{OUTSENSE1–} = ±500mV (Notes 5, 7)
T_A = 0°C to 85°C
T_A = –40°C to 125°C
l 0.594 0.6 0.606
V
l 0.591 0.6 0.609
V
VTTSNS(REG) Regulated Voltage Error on Channel 2,
VTTSNS (Referenced to VTTR)
ITH2 = 1.4V (Note 5)
T_A = 0°C to 85°C
T_A = –40°C to 125°C
l –10
l –15
10
mV
15
mV
I_VOUTSENSE1+
I_{VOUTSENSE1–}
Regulated Voltage Error on Channel 2,
VTTSNS Over Line, Load and Common
Mode. (Referenced to VTTR)
V_OUTSENSE1+ Input Bias Current
V_{OUTSENSE1–} Input Bias Current
V_IN = 4.5V to 38V, ITH1 = 0.5V to 1.9V,
(Notes 5, 7)
T_A = 0°C to 85°C
T_A = –40°C to 125°C
V_DFB1 [V_OUTSENSE1+ – V_{OUTSENSE1–}] = 0.6V
V_DFB1 [V_OUTSENSE1+ – V_{OUTSENSE1–}] = 0.6V
l –15
l –20
15
mV
20
mV
±5
±25
nA
–25 –50
μA
I_VTTSNS
I_VTTSNS Input Bias Current
I_VTTSNS = 750mV
±5
±50
nA
g_m(EA)1,2
t_ON(MIN)1,2
Error Amplifier Transconductance
Minimum On-Time
ITH = 1.2V (Note 3)
V_IN = 38V, R_T = 20k, VDDSNS = 1.2V, V_SENSE– = 0.6V
1.7
mS
30
ns
t_OFF(MIN)1,2
Minimum Off-Time
90
ns
Current Sensing
V_SENSE1(MAX) Maximum Valley Current Sense Threshold V_RNG = 2V, V_DFB1 = 0.57V, V_SENSE1– = 1.5V
l 80 100 120 mV
(V_SENSE1+ – V_SENSE1–)
V_RNG
V_RNG
=
=
0INV,TVV_{CDCFB, 1VD}=_F0_B.₁5=7V0,.V57_{SEVN, SVES1E–N}=_SE1₁._–5=V
1.5V
l 21
l 39
30
50
40
61
mV
mV
V_SENSE1(MIN)
Minimum Valley Current Sense Threshold
(V_SENSE1+ – V_SENSE1–)
(Forced Continuous Mode)
V_RNG
V_RNG
V_RNG
=
=
=
20INVV,,TVVV_{CDDCFFBB, 11VD}==_F00_B..₁66=33VV0,,.VV63_{SSEEVNN, SSVEES11E––N}==_SE11₁.._–55=VV
1.5V
–50
mV
–15
mV
–25
mV
V_SENSE2(MAX)
Maximum Valley Current Sense Threshold
(V_SENSE2+ – V_SENSE2–)
V_RNG
V_RNG
=
=
2V,
0V,
VTTSNS
VTTSNS
=
=
0.72V,
0.72V,
VV_{SSEENNSSEE22––}
=
=
0.75V
0.75V
l 80 100 120 mV
l 21
30
40
mV
V_RNG = INTV_CC, VTTSNS = 0.72V, V_SENSE2– = 0.75V l 39
50
61
mV
V_SENSE2(MIN)
Minimum Valley Current Sense Threshold V_RNG = 2V, VTTSNS = 0.78V, V_SENSE2– = 0.75V
(V_SENSE1+ – V_SENSE1–)
V_RNG = 0V, VTTSNS = 0.78V, V_SENSE2– = 0.75V
(Forced Continuous Mode)
V_RNG = INTV_CC, VTTSNS = 0.78V, V_SENSE2– = 0.75V
–120
mV
–36
mV
–60
mV
I_SENSE1,2+
SENSE1,2⁺ Pins Input Bias Current
V_SENSE+ = 0.6V
V_SENSE+ = 2.5V
±5
±50
nA
1
±2
μA
I_{SENSE1,2–}
SENSE2^– Pins Input Bias Current
(Internal 500k Resistor to SGND)
V_SENSE1– = 0.6V
V_SENSE1– = 2.5V
1.2
μA
5
μA
3876f
3