LTC3876_15 Datasheet, PDF (39/48 Pages) Linear Technology – Dual DC/DC Controller for DDR Power with Differential VDDQ Sensing and 50mA VTT Reference

LTC3876
APPLICATIONS INFORMATION
PCB Layout Checklist
The printed circuit board layout is illustrated graphically
in Figure 12. Use the following checklist to ensure proper
operation of the LTC3876:
• A multilayer printed circuit board with dedicated ground
planes is generally preferred to reduce noise coupling
and improve heat sinking. The ground plane layer
should be immediately next to the routing layer for the
power components, e.g., MOSFETs, inductors, sense
resistors, input and output capacitors etc.
• Keep SGND and PGND separate. Upon finishing the
layout, connect SGND and PGND together with a single
PCB trace underneath the IC from the SGND pin through
the exposed PGND pad to the PGND pin.
• All power train components should be referenced to
PGND; all components connected to noise-sensitive
pins, e.g., ITH, RT, TRACK/SS and V_RNG, should return
to the SGND pin. Keep PGND ample, but SGND area
compact. Use a modified “star ground” technique: a low
impedance, large copper area central PCB point on the
same side of the as the input and output capacitors.
• Place power components, such as C_IN, C_OUT, MOSFETs,
D_B and inductors, in one compact area. Use wide but
shortest possible traces for high current paths (e.g.,
V_IN, V_OUT, PGND etc.) to this area to minimize copper
loss.
• Keep the switch nodes (SW1,2), top gates (TG1,2) and
boost nodes (BOOST1,2) away from noise-sensitive
small-signal nodes, especially from the opposite
channel’s voltage and current sensing feedback pins.
These nodes have very large and fast moving signals
and therefore should be kept on the “output side” of
the LTC3876 (power-related pins are toward the right
hand side of the IC), and occupy minimum PC trace
area. Use compact switch node (SW) planes to improve
cooling of the MOSFETs and to keep EMI down. If DCR
sensing is used, place the top filter resistor (R1 only in
Figure 5) close to the switch node.
• The top N-channel MOSFETs of the two channels have
to be located within a short distance from (preferably
<1cm) each other with a common drain connection at
C_IN. Do not attempt to split the input decoupling for the
two channels as it can result in a large resonant loop.
• Connect the input capacitor(s), C_IN, close to the power
MOSFETs. This capacitor provides the MOSFET transient
spike current. Connect the drain of the top MOSFET as
close as possible to the (+) plate of the ceramic portion
of input capacitors C_IN. Connect the source of the bot-
tom MOSFET as close as possible to the (–) terminal
of the same ceramic C_IN capacitor(s). These ceramic
capacitor(s) bypass the high di/dt current locally, and
both top and bottom MOSFET should have short PCB
trace lengths to minimize high frequency EMI and
prevent MOSFET voltage stress from inductive ringing.
• The path formed by the top and bottom N-channel
MOSFETs, and the C_IN capacitors should have short
leads and PCB trace. The (–) terminal of output capaci-
tors should be connected close to the (–) terminal of
C_IN, but away from the loop described above. This is
to achieve an effect of Kevin (4-wire) connection to the
input ground so that the “chopped” switching current
will not flow through the path between the input ground
and the output ground, and cause common mode output
voltage ripple.
• Several smaller sized ceramic output capacitors, C_OUT,
can be placed close to the sense resistors and before
the rest bulk output capacitors.
• The filter capacitor between the SENSE⁺ and SENSE^– pins
should always be as close as possible to these pins.
Ensure accurate current sensing with Kevin (4-wire)
connections to the soldering pads from underneath
the sense resistors or inductor. A pair of sense traces
should be routed together with minimum spacing.
R_SENSE, if used, should be connected to the inductor
on the noiseless output side, and its filter resistors
close to the SENSE⁺/SENSE^– pins. For DCR sensing,
however, filter resistor should be placed close to the
inductor, and away from the SENSE⁺/SENSE^– pins, as
its terminal is the SW node.
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