LTC3876_15 Datasheet, PDF (10/48 Pages) Linear Technology – Dual DC/DC Controller for DDR Power with Differential VDDQ Sensing and 50mA VTT Reference

LTC3876
PIN FUNCTIONS (QFN/TSSOP)
ITH2 (Pin 1/Pin 5): Channel 2 VTT Current Control
Threshold. This pin is the output of the error amplifier
and the switching regulator’s compensation point. The
current comparator threshold increases with this control
voltage. This voltage ranges from 0V to 2.2V. ITH2 has
been optimized to support a symmetric range of positive
and negative current by moving the zero sense voltage to
1.2V. (zero inductor valley current).
VDDQSNS (Pin 2/Pin 6): VDDQ Sense. VDDQSNS
provides the VDDQ regulation reference point to the
VTT differential reference resistor divider. The positive
Input to the VTT differential reference resistor divider is
VDDQSNS and negative input is V_{OUTSENSE–}. The resistor
divider is connected internally between VDDQSNS and
V_{OUTSENSE–} and is composed of two equally sized 105k
resistors in series for 210K total resistance.
When VDDQSNS is tied to INTV_CC, the VTTR linear reference
outputs are three-stated and VTTR becomes the VTTSNS
reference input. This allows the option to tie the VTTR
reference input to the VTTR output of a second LTC3876
in a multiphase application.
VTTR (Pin 3/Pin 7): VTT Reference. VTTR is the buffered
output of the VTT differential reference resistor divider.
VTTR is specifically designed for large DDR memory
systems by providing superior accuracy and load regula-
tion specified for up to ±50mA. Connect VTTR directly to
the DDR memory V_REF input. VTTR is a high output linear
reference which tracks the VTT differential reference resis-
tor divider and is equal to 0.5 • (VDDQSNS – V_{OUTSENSE–}).
Power is supplied through VTTRVCC. Internally the VTTR
connection is connected to VDDQSNS reference in order
to provide Kelvin sensing of VTTR. The output capacitor
minimum should be 2.2μF.
VTTRVCC (Pin 4/Pin 8): VTTR Supply Input for VTTR
Reference. Connect to DRV_CC through an RC decoupling
filter of 2.2μF and 1Ω typically.
MODE/PLLIN (Pin 5/Pin 9): Operation Mode Selection
or External Clock Synchronization Input. When this pin
is tied to INTV_CC forced continuous mode operation is
selected. Typing this pin to SGND allows discontinuous
mode operation on channel 1, VDDQ while channel 2, VTT
operates in forced continuous mode. When an external
clock is applied at this pin, both channels operate in forced
continuous mode and are synchronized to the external
clock. Channel 2 VTT operates in forced continuous mode
only; permitting it to accurately track VTTR when sourcing
and sinking load current.
CLKOUT (Pin 6/Pin 10): Clock Output of Internal Clock
Generator. Its output level swings between INTV_CC and
SGND. If clock input is present at the MODE/PLLIN pin,
it will be synchronized to the input clock, with phase set
by the PHASMD pin. If no clock is present at the MODE/
PLLIN pin, its frequency will be set by the RT pin. To syn-
chronize other controllers, CLKOUT can be connected to
their MODE/PLLIN pins.
SGND (Pin 7/Pin 11): Signal Ground. All small-signal
analog components should be connected to this ground.
Connect SGND to the exposed pad and PGND pin using
a single PCB trace.
RT (Pin 8/Pin 12): Clock Generator Frequency Program-
ming Pin. Connect an external resistor from RT to SGND
to program the switching frequency between 200kHz and
2MHz. An external clock applied to MODE/PLLIN should
be within ±30% of this programmed frequency to ensure
frequency lock. When the RT pin is floating, the frequency
is internally set to be slightly under 200kHz.
V_RNG1, V_RNG2 (Pin 9, Pin 34/Pin 13, Pin 38): Current
Sense Voltage Range Inputs. When programmed between
0.6V and 2V, the voltage applied to V_RNG1,2 is twenty times
(20x) the maximum sense voltage between SENSE1,2⁺ and
SENSE1,2^–, i.e., for either channel, (V_SENSE+ – V_SENSE–) =
0.5 • V_RNG. If a V_RNG is tied to SGND the channel operates
with a maximum sense voltage of 30mV, equivalent to a
V_RNG of 0.6V; If tied to INTV_CC, a maximum sense voltage
of 50mV, equivalent to a V_RNG of 1V. Do not float these pins.
ITH1 (Pin 10/Pin 14): Channel 1 VDDQ Current Control
Threshold. This pin is the output of the error amplifier
and the switching regulator’s compensation point. The
current comparator threshold increases with this control
voltage. The voltage ranges from 0V to 2.4V, with 0.8V
corresponding to the zero sense voltage (zero inductor
valley current).
3876f
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