LTC3876_15 Datasheet, PDF (38/48 Pages) Linear Technology – Dual DC/DC Controller for DDR Power with Differential VDDQ Sensing and 50mA VTT Reference

LTC3876
APPLICATIONS INFORMATION
The DCR sense filter is designed using a simple RC filter
across the inductor. If the inductor value and DCR is known,
choose a sense filter C and calculate filter resistance.
Channel 1 DCR filter resistor R_DCR1:
R_DCR1
=
L1
DCR •C_DCR
=
0.47μH
0.8mΩ • 0.1μF
=
5.9k
Channel 2 DCR filter resistor R_DCR2:
R_DCR1
=
L1
DCR •C_DCR
=
0.47μH
1.72mΩ • 0.1μF
=
2.74k
The external N-channel MOSFETs are chosen based
on current capability and efficiency. The Renesas
RJK0305DBP (R_DS(ON) = 13mΩ(maximum), C_MILLER = 150pF,
VGS = 4.5V, V_MILLER = 3V, θ_JA = 40°C/W, T_J(MAX) = 150°C)
is chosen for the top MOSFET (main switch). The Renesas
RJK0330DBP (R_DS(ON) = 3.9mΩ(maximum), V_GS = 4.5V,
θ_JA = 40°C/W, T_J(MAX) =150°C) is chosen for the bottom
MOSFET (synchronous switch).The power dissipation for
each MOSFET can be calculated for V_IN = 14V and typical
T_J =125°C.
The power dissipation for V_IN = 14V and T_J =125°C for
the top MOSFET is:
P_TOP
=
1.5V
14V
(20A)²
(1+
0.4%(125°C–25°C))
(0.013Ω)
+
(14V)²
⎛⎝⎜_202A⎞⎠⎟
(150pF)
⎛⎝⎜_{5.32V.5–Ω3V}
+
1.2Ω^⎞⎟
3V ⎠
(400kHz)
= 0.78W + 0.17W = 0.95W
The power dissipation for V_IN = 14V and T_J =125°C for
2X bottom MOSFETs is:
P_BOT
=
14V – 1.5V
14V
⎛⎝⎜_220XA⎞⎠⎟
2
(1+ 0.4%(125°C – 25°C))(0.0039Ω) = 0.4875W
The resulting junction temperatures for ambient tempera-
ture T_A = 75°C are:
T_J(TOP) = 75°C + (0.95W)(40°C/W) = 113°C
T_J(BOT) = 75°C + (0.975W)(40°C/W) = 94.5°C
These numbers show that careful attention should be paid
to proper heat sinking when operating at higher ambient
temperatures.
Select C_IN capacitors to give ample capacitance and RMS
ripple current rating. Consider worst-case duty cycles per
Figure 6. If operated at steady-state with SW nodes fully
interleaved, the two channels would generate not more
than 7.5A RMS at full load. In this design example, 2X
10μF 25V X5R ceramic capacitors are put in parallel to take
the RMS ripple current with 330μF aluminum electrolytic
bulk capacitors for stability. For 10μF 1210 X5R ceramic
capacitors, try to keep the ripple current less than 3A RMS
through each device. The bulk capacitor is chosen for
RMS rating per simulation with the circuit model provided.
The power supply output capacitor’s C_OUT are chosen
for a low ESR. For channel 1 VDDQ, the output capacitor
SANYO 2R5TPE330M9, has an ESR of 9mΩ which results
in 4.5mΩ for two in parallel. For channel 2 VTT, the output
capacitor SANYO 2R5TPE330M9, has an ESR of 9mΩ.
The output ripple for each channel is given as:
ΔVDDQ(RIPPLE) = ΔI_L(MAX) (ESR)
= (7.12A) • (4.5mΩ) = 32mV
ΔVTT(RIPPLE) = ΔI_L(MAX) (ESR)
= (3.78A) • (9mΩ) = 34mV
A 0A to 10A load step in VDDQ will cause an output change
of up to:
ΔVDDQ(STEP) = ΔI_LOAD (ESR) = 10A • 0.0045mΩ =
45mV
A 0A to 5A load step in VTT will cause an output change
of up to:
ΔVTT(STEP) = ΔI_LOAD (ESR) = 5A • 0.009mΩ = 45mV
Optional 100μF ceramic output capacitors are included
to minimize the effect of ESL in the output ripple and to
improve load step response.
3876f
38