LTC3876_15 Datasheet, PDF (13/48 Pages) Linear Technology – Dual DC/DC Controller for DDR Power with Differential VDDQ Sensing and 50mA VTT Reference

LTC3876
FUNCTIONAL DIAGRAM
2μA
TO 5μA
PTAT
10μA
RUN
+
1.2V –
+
UVLO
EN_DRV
V_IN
IN
EN LDO
OUT SD
4.2V
V_IN
TG
BOOST
DRV
TG
SW
D_B
C_B
M_T
L
R_SENSE
VTT
CHANNEL 2
EXTV_CC
DRV_CC
VDDQ
CHANNEL 1
0.7V –
LOGIC
CONTROL
SENSE^–
V_IN
250k
ONE-SHOT
TIMER
START
STOP
MODE/PLLIN
FORCED
CONTINUOUS
MODE
MODE/CLK
DETECT
250k
ON-TIME
ADJUST
PHASE
DETECTOR
RT
R_T
CLK1
CLOCK PLL/
GENERATOR ^CLK2
TO CHANNEL 2
I_CMP
+–
I_REV
+–
CLKOUT
INTV_CC
R_PGD
PGOOD
DELAY
OV
CH1
UV
g_m
g_m
1μA
EA1
0.6V
4.7V
INTV_CC
DRV_CC2
DRV_CC1
BG DRV
BG
PGND
C_INTVCC
C_DRVCC
M_B
C_OUT
R_FB1
R_FB2
SENSE⁺
SENSE^–
CVCC
INTV_CC
TRACK/SS
DIFFAMP
(A = 1)
V_OUTSENSE1+
V_{OUTSENSE1–}
C_SS
105k
105k
VDDQSNS
DRV_CC
OV
CH2
UV
DUPLICATE DASHED
LINE BOX FOR
CHANNEL 2
V_RNG
ITH
INTV_CC
1/2 INTV_CC
+
–
DTR
LOAD
RELEASE
DETECTION
TO LOGIC
CONTROL
VTTRVCC
EA2
CHANNEL 2
VTTR
VTTSNS
C_VTTR(VCC)
C_VTTR
3876 FD
INTV_CC
INTV_CC
C_ITH1
R_ITH2
C_ITH2 ^RITH1
3876f
13