LTC3876_15 Datasheet, PDF (36/48 Pages) Linear Technology – Dual DC/DC Controller for DDR Power with Differential VDDQ Sensing and 50mA VTT Reference

LTC3876
APPLICATIONS INFORMATION
source will scale the V_IN current required for the driver
and controller circuits by a factor of (duty cycle)/(ef-
ficiency). For example, in a 20V to 5V application, 10mA
of DRV_CC current results in approximately 2.5mA of V_IN
current. This reduces the mid-current loss from 10%
or more (if the driver was powered directly from V_IN)
to only a few percent.
4. C_IN loss. The input capacitor filters large square-wave
input current drawn by the regulator into an averaged
DC current from the supply. The capacitor itself has
a zero average DC current, but square-wave-like AC
current flows through it. Therefore the input capacitor
must have a very low ESR to minimize the RMS current
loss on ESR. It must also have sufficient capacitance
to filter out the AC component of the input current to
prevent additional RMS losses in upstream cabling,
fuses or batteries. The LTC3876 2-phase architecture
improves the ESR loss.
“Hidden” copper trace, fuse and battery resistance, even
at DC current, can cause a significant amount of efficiency
degradation, so it is important to consider them during
the design phase. Other losses, which include the C_OUT
ESR loss, bottom MOSFET’s body diode reverse-recovery
loss, and inductor core loss generally account for less
than 2% additional loss.
Power losses in the switching regulator will reflect as
a higher than ideal duty cycle, or a longer on-time for a
constant frequency. This efficiency accounted on-time
can be calculated as:
t_ON ≈ t_ON(IDEAL)/Efficiency
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased.
Design Example
The following design example is the DDR3 application
circuit as implemented on the standard LTC3876 QFN
demo board 1631A. This DC/DC step-down converter
design accommodates an input V_IN range of 4.5V to 14V,
with a VDDQ output of 1.5V and a VTT output of 0.75V.
The DDRIII output channels are designed to produce 1.5V
36
VDDQ at 20A, a 0.75V VTT 10A maximum average operat-
ing current with a VTT reference output (VTTR) capable of
supplying up to ±50mA. (see Figure 11, LTC3876 demo
circuit 1631A)
The regulated channel 1 VDDQ output supply voltage is
determined by:
VDDQ = 0.6V ^⎛1+ ^{RFB2 ⎞}
⎝ ^R_FB1 ⎠
Set VDDQ to 1.5V for DDRIII application. Using a 20k
resistor for R_FB1, the resulting R_BF2 is 30k.
The regulated channel 2 VTT termination supply is differ-
entially referenced to an internal resistor divider connected
between the VDDQSNS and the V_{OUTSENSE–}. The resulting
differential VTT reference output (VTTR) is one-half VDDQ
which in this design example is 0.75V. The VTT termina-
tion supply nominally regulates to 0.75V and will track
any dynamic movement of the channel 1 VDDQ supply.
The switching frequency for both channels is programmed
by:
R_T
[kΩ
]
=
4
•
41550
f[kHz]
–
2.2
For f = 400kHz, R_T = 102kΩ.
The minimum on-time occurs for maximum V_IN and
should be greater than the typical minimum of 30ns with
adequate margin. The minimum on-time margin should
allow for device variability and the extension of effective
on-time at light load due to the dead times. The reason
for the on-time extension at light load is that the negative
inductor current causes the switch node to rise which
effectively adds to the on time. This is of limited concern
to the channel 1 VDDQ but is of greater concern to the
channel 2 VTT supply because it supplies significant
negative current. For the LTC3876 the minimum on-time
without any extension is 30ns, with driver dead times of
30ns. For strong negative currents in VTT the total dead
time is the total of the minimum on-time, plus both dead
times for 90ns. It is therefore recommended to keep the
minimum on-time greater than 100ns for channel 2 VTT
to assure PLL lock under all operating conditions.
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