LTC3876_15 Datasheet, PDF (33/48 Pages) Linear Technology – Dual DC/DC Controller for DDR Power with Differential VDDQ Sensing and 50mA VTT Reference

LTC3876
APPLICATIONS INFORMATION
Worst-case efficiency typically occurs at the highest V_IN
and highest ambient temperature. It is important to check
for consistency between the assumed MOSFET junction
temperatures and the resulting value of I_LIMIT which heats
the MOSFET switches.
To further limit current in the event of a short circuit to
ground, the LTC3876 includes foldback current limiting.
If the output falls by more than 50%, the maximum sense
voltage is progressively lowered, to about one-fourth of
its full value as the feedback voltage reaches 0V.
A feedback voltage exceeding 7.5% for VDDQ channel 1
and 10% for VTT channel 2 of the regulated target of
0.6V is considered as overvoltage (OV). In such an OV
condition, the top MOSFET is immediately turned off and
the bottom MOSFET is turned on indefinitely until the OV
condition is removed, i.e., the feedback voltage falling
back below the threshold by more than a hysteresis of
typical 15mV. Current limiting is not active during an OV.
If the OV persists, and the BG turns on for a longer time,
the current through the inductor and the bottom MOSFET
may exceed their maximum ratings, sacrificing themselves
to protect the load.
OPTI-LOOP Compensation
OPTI-LOOP^® compensation, through the availability of the
ITH pin, allows the transient response to be optimized for
a wide range of loads and output capacitors. The ITH pin
not only allows optimization of the control-loop behavior
but also provides a DC-coupled and AC-filtered closed-loop
response test point. The DC step, rise time and settling
at this test point truly reflects the closed-loop response.
Assuming a predominantly 2nd order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin.
The external series R_ITH-C_ITH1 filter at the ITH pin sets the
dominant pole-zero loop compensation. The values can
be adjusted to optimize transient response once the final
PCB layout is done and the particular output capacitor type
and value have been determined. The output capacitors
need to be selected first because their various types and
values determine the loop feedback factor gain and phase.
An additional small capacitor, C_ITH2, can be placed from
the ITH pin to SGND to attenuate high frequency noise.
Note this C_ITH2 contributes an additional pole in the loop
gain therefore can affect system stability if too large. It
should be chosen so that the added pole is higher than
the loop bandwidth by a significant margin.
The regulator loop response can also be checked by
looking at the load transient response. An output current
pulse of 20% to 100% of full-load current having a rise
time of 1μs to 10μs will produce V_OUT and ITH voltage
transient-response waveforms that can give a sense of the
overall loop stability without breaking the feedback loop.
For a detailed explanation of OPTI-LOOP compensation,
refer to Application Note 76.
Switching regulators take several cycles to respond to
a step in load current. When a load step occurs, V_OUT
immediately shifts by an amount equal to ∆I_LOAD • ESR,
where ESR is the effective series resistance of C_OUT. ∆I_LOAD
also begins to charge or discharge C_OUT, generating a
feedback error signal used by the regulator to return V_OUT
to its steady-state value. During this recovery time, V_OUT
can be monitored for overshoot or ringing that would
indicate a stability problem.
Connecting a resistive load in series with a power MOSFET,
then placing the two directly across the output capacitor
and driving the gate with an appropriate signal generator
is a practical way to produce a realistic load step condi-
tion. The initial output voltage step resulting from the step
change in load current may not be within the bandwidth
of the feedback loop, so it cannot be used to determine
phase margin. The output voltage settling behavior is more
related to the stability of the closed-loop system. However,
it is better to look at the filtered and compensated feedback
loop response at the ITH pin.
The gain of the loop increases with the R_ITH and the band-
width of the loop increases with decreasing C_ITH1. If R_ITH
is increased by the same factor that C_ITH1 is decreased, the
zero frequency will be kept the same, thereby keeping the
phase the same in the most critical frequency range of the
feedback loop. In addition, a feedforward capacitor, C_FF,
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