LTC3876_15 Datasheet, PDF (31/48 Pages) Linear Technology – Dual DC/DC Controller for DDR Power with Differential VDDQ Sensing and 50mA VTT Reference

LTC3876
APPLICATIONS INFORMATION
If an application requires very low (approaching minimum)
on-time, the system may not be able to maintain its full
frequency synchronization range. Getting closer to mini-
mum on-time, it may even lose phase/frequency lock at no
load or light load conditions, under which the SW on-time
is effectively longer than TG on-time due to TG/BG dead
times. This is discussed further under Minimum On-Time,
Minimum Off-Time and Dropout Operation.
Minimum On-Time, Minimum Off-Time
and Dropout Operation
The minimum on-time is the smallest duration that
LTC3876’s TG (top gate) pin can be in high or “on” state.
It has dependency on the operating conditions of the
switching regulator, and is a function of voltages on the
V_IN and V_OUT pins, as well as the value of external resistor
R_T. A minimum on-time of 30ns can be achieved when the
V_OUT pin is tied to its minimum value of 0.6V while the V_IN
is tied to its maximum value of 38V. For larger values of
V_OUT and/or smaller values of V_IN, the minimum achievable
on-time will be longer. The valley mode control architecture
allows low on-time, making the LTC3876 suitable for high
step-down ratio applications.
The effective on-time, as determined by the SW node
pulse width, can be different from this TG on-time, as it
also depends on external components, as well as loading
conditions of the switching regulator. One of the factors that
contributes to this discrepancy is the characteristics of the
power MOSFETs. For example, if the top power MOSFET’s
turn-on delay is much smaller than the turn-off delay,
the effective on-time will be longer than the TG on-time,
limiting the effective minimum on-time to a larger value.
Light-load operation, in forced continuous mode, will
further elongate the effective on-time due to the dead
times between the “on” states of TG and BG, as shown in
Figure 10. During the dead time from BG turn-off to TG
turn-on, the inductor current flows in the reverse direction,
charging the SW node high before the TG actually turns
on. The reverse current is typically small, causing a slow
rising edge. On the falling edge, after the top FET turns off
and before the bottom FET turns on, the SW node lingers
high for a longer duration due to a smaller peak inductor
current available in light load to pull the SW node low. As
a result of the sluggish SW node rising and falling edges,
the effective on-time is extended and not fully controlled
by the TG on-time. Closer to minimum on-time, this may
cause some phase jitter to appear at light load. As load
current increase, the edges become sharper, and the phase
locking behavior improves.
The minimum on-time of the VTT channel is further limited
by the fact that it must support negative current operation.
Both the TG to BG and BG to TG dead-time delays add
TG-SW
(V_GS OF TOP
MOSFET)
BG
(V_GS OF
BOTTOM
MOSFET)
DEAD-TIME
DELAYS
I_L 0
V_IN
SW
NEGATIVE
INDUCTOR
CURRENT
IN FCM
3876 F10
DURING BG-TG DEAD TIME,
NEGATIVE INDUCTOR CURRENT
WILL FLOW THROUGH TOP MOSFET’S
BODY DIODE TO PRECHARGE SW NODE
I_L
+– _VIN
DURING TG-BG DEAD TIME,
THE RATE OF SW NODE DISCHARGE
WILL DEPEND ON THE CAPACITANCE
ON THE SW NODE AND INDUCTOR
CURRENT MAGNITUDE
L
L
SW
I_L
TOTAL CAPACITANCE
ON THE SW NODE
Figure 10. Light Loading On-Time Extension for Forced
Continuous Mode Operation
3876f
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