LTC3876_15 Datasheet, PDF (14/48 Pages) Linear Technology – Dual DC/DC Controller for DDR Power with Differential VDDQ Sensing and 50mA VTT Reference

LTC3876
OPERATION (Refer to Functional Diagram)
DDR Operation
The LTC3876 is a dual channel, current mode step-down
controller designed to provide high efficiency power con-
version for high power DDR memory and bus termination
supplies. Its unique controlled on-time architecture allows
extremely low step-down ratio’s while maintaining a fast,
constant switching frequency.
The LTC3876 is a complete DDR power solution with one
master RUN pin, TRACK/SS input and PGOOD output.
The RUN pin enables all supplies. The TRACK/SS pin
determines the VDDQ soft-start characteristics and VTT
tracks 0.5 • VDDQ. PGOOD monitors both VDDQ and
VTT to ensure regulation within a ±7.5% typical window.
The current limit settings are set independently on both
VDDQ and VTT channels. The VDDQ, VTT and CLKOUT
phase relationships are set by the PHASMD pin to permit
multiphase operation in high power DDR solutions which
require more than one VDDQ or VTT channel.
VDDQ Supply
The LTC3876 is designed to support any DDR applica-
tion where VDDQ can range from 2.5V down to 1V. The
LTC3876 supports high power applications by differentially
regulating the VDDQ supply, VTTR reference and VTT sup-
ply. The channel 1 feedback resistor divider, VDDQSNS
and V_{OUTSENSE–} should be tied directly to the differential
VDDQ regulation points. For best results these connec-
tions should be routed separately and Kelvin connected.
VDDQSNS is the VDDQ regulation sense point or positive
input and V_{OUTSENSE–} is the remote ground sense point
or negative input to the VTT differential reference resistor
divider. The resistor divider is connected internally between
VDDQSNS and V_{OUTSENSE–} and is composed of two equally
sized 105k resistors in series for 210K total resistance.
VTT Supply
The VTT supply reference is connected internally to the
output of the VTTR VTT reference output. VTTSNS provides
the inverting regulation feedback signal for the VTT ter-
mination supply. Kelvin-connect the VTTSNS pin directly
to desired regulation point on the VTT supply. By sensing
VTTSNS the channel 2 VTT supply regulates to VTTR.
The VTT supply operates in forced continuous mode and
tracks VDDQ in start-up and in normal operation regardless
of the MODE/PLLIN settings. In start-up the VTT supply is
enabled coincident with the VDDQ supply. Operating the
VTT supply in forced continuous allows accurate tracking
in startup and under all operating conditions.
VTT Reference (VTTR)
The linear VTT reference, VTTR, is specifically designed
for large DDR memory systems by providing superior
accuracy and load regulation for up to ±50mA output
load. VTTR is the buffered output of the VTT differential
reference resistor divider.
VTTR is a high output linear reference which tracks the
VTT differential reference resistor divider and is equal to
0.5 • (VDDQSNS – V_{OUTSENSE–}). Connect VTTR directly to
the DDR memory V_REF input. Power is supplied through
VTTRVCC. Internally the VTTR connection is connected to
VDDQSNS reference to provide Kelvin sensing of VTTR.
Both input and output supply decoupling is important to
performance and accuracy. A 2.2μF output capacitor is
recommended for most typical applications. It is suggested
to use no less than 1μF and no more than 47μF on the
VTTR output. The typical recommended input VTTRVCC
RC decoupling filter is 2.2μF and 1Ω.
When VDDQSNS is tied to INTV_CC, the VTTR linear
reference output is three-stated and VTTR becomes the
VTTSNS reference input. This allows the option to tie the
VTTR reference input to the VTTR output of a second
LTC3876 in a multiphase application.
Main Control Loop
The LTC3876 is a controlled on-time, valley current mode
step-down DC/DC dual controller with two channels op-
erating out of phase. Each channel drives both main and
synchronous N-channel MOSFETs. The two channels oper-
ate independently where channel 1 is VDDQ and channel 2
is the VTT termination supply which tracks 0.5 • VDDQ.
The top MOSFET is turned on for a time interval deter-
mined by a one-shot timer. The one-shot timer or the top
MOSFET’s on-time is controlled to maintain a fixed switch-
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