81250 Datasheet, PDF (8/64 Pages) Keysight Technologies – Agilent ParBERT 81250 Parallel Bit Error Ratio Tester

Different data rates
The architecture of
ParBERT 81250 allows using
data modules of different speed
classes in one clock group.
Choosing the right combination
of system data rate and binary
frequency multipliers (…, 1/16,
1/8, 1/4, 1/2, 1 , 2 ,4 ,8 , 16, …)
enables each module to operate
within its valid data rate range.
Furthermore even channels
within one module can operate
at different data rates of binary
ratio (see figure 8).
ParBERT can be configured with
one or more clock groups each
controlled via an independent
instance of the GUI. The clock
groups can either run completely
independent from each other or
can be locked to each other in a
frequency ratio of m/n, with
m, n=1…256 and m x n<1024.
In chapter "ParBERT 81250
application examples" on page 17
some configurations with two
clock groups are shown.
Jitter injection and spread
spectrum clocking SSC
Receiver margining is a
measurement that is very
demanding in terms of signal
conditioning capabilities of the
stimulating pattern generator,
because it shall emulate worst
case conditions as they may
appear in mission mode of the
DUT or as they are specified in
relevant standards. For this
purpose not only voltage levels
and cross point of differential
signals shall be adjustable. Jitter
shall be injected as well. For this
purpose the higher data rate
modules of ParBERT, i.e. the
3.35 Gb/s, 7Gb/s and 13.5 Gb/s
generator modules are equipped
with a delay control input, that
allows phase modulation of the
data output signals equivalent to
the applied voltage signal.
Modern computer standards use
spread spectrum clocking (SSC)
techniques to decrease the power
density of radiated emissions per
frequency. The 13.5 GHz clock
module allows direct feed-through
of such a multi-UI low frequency
modulated external clock
enabling the data modules to
generate and analyze such data
patterns with SSC. Agilent's
signal generators can be used to
generate such a modulated clock.
Figure 8. Parameter editor for setting multiple frequencies in one system
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