81250 Datasheet, PDF (51/64 Pages) Keysight Technologies – Agilent ParBERT 81250 Parallel Bit Error Ratio Tester

Timing capabilities
Start input
The E4809A supports three
different operation modes.
A sequence of generated data can
be started by an external signal.
E4809A as system clock
The E4809A distributes clock
signals to connected modules in
the range from 20.834 MHz up to
13.5 GHz. The E4809A provides
Giga-clock signals in a range
from 500 MHz up to 13.5 GHz to
the ParBERT 81250 13.5 Gb/s
modules (N4872A, N4873A). All
other supported modules work
using the E4809A master clock.
External clock mode
The system will run synchro-
nously to an external clock,
which is connected to the clock
module's clock input. There are
two different sub-modes availa-
ble. In the direct clock mode, the
PLL (phase locked loop) is
bypassed and an external clock
signal can be distributed to all
Giga-clock connected modules.
This direct external clock mode
operates in a range from 500 MHz
to 13.5 GHz. In this mode the
external clock may be FM or
PM modulated. In the indirect
external clock mode, the clock
modules’ internal PLL is used to
generate flexible master clock
and Giga-clock signals.
Table 63. Start input
Start input
Threshold range
Zin/termination voltage
Sensitivity/max. levels
DC coupled; 3.5 mm (f)
–1.40 V to +3,70 V
50 Ω typ./-2 V to +3 V
200 mVpp / -3 V…+6 V
Reference input
The reference input allows
ParBERT to run synchronously
with an external 10 MHz clock. A
continuous clock is necessary. A
burst clock can not be used as an
external clock.
TTable 64. Reference input
Reference input
Frequency
Input transition time
Required duty cycle
Imput impedence
Sensitivity
Required input phase noise
AC coupled; 3.5 mm(f)
10 MHz
< 20 ns
50% ±10
50 Ω
200 mVpp
<–137 dBc @ 10 MHz offset
Clock data recovery (CDR) mode
If the CDR is used, the CDR out
of the analyzer must be connect-
ed to the clock input of the clock
module.
ParBERT 81250 Main Overview
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