81250 Datasheet, PDF (22/64 Pages) Keysight Technologies – Agilent ParBERT 81250 Parallel Bit Error Ratio Tester

PCI Express
PCIe shall be used as an
application example from the
computer industry. This bus
consists of up to 16 differential
point to point connections, so
called lanes. Architectural it is
not a traditional synchronous,
parallel bus instead a multiple
serial bus. Symbol rates are
2.5Gb/s, 5Gb/s and 8Gb/s for the
three generations of the standard
already defined or in process.
Generation 1 and 2 use 8B/10B
coding with a relatively high
overhead of 25%. For the third
generation this coding scheme
was dropped because of its data
rate penalty.
For the first generation with its
moderate symbol rate of 2.5Gb/s
an RX test was not defined. This
has changed since the second
generation, where for RX jitter
tolerance test, a quite complicated
cocktail was defined. While a
single lane can be tested with a
serial BERT such as the Agilent
N4903 J-BERT, an extensive and
more realistic simultaneous test
of more than one lane can only
be achieved with a ParBERT. In
order to generate test patterns
with the required jitter cocktail
ParBERT makes use of its jitter
modulation capability via the
external delay control input.
Figure 19 shows a setup with
Agilent 33220 and 81150A acting
as jitter modulation sources. The
whole setup is structured into
three clock groups. The first with
the 33250 being connected “only”
generates a modulated clock that
the second ParBERT system runs
from. With the help of the 81150A
and an accessory filter the random
jitter RJ with the required spectral
distribution is created. The third
clock group holds ParBERT
analyzers that by measuring
BER check if the RX under test
tolerated the amount of jitter
applied at its input and extracted
the data content correctly, i.e. with
a BER below the specified limit.
Specified test patterns can be
created utilizing ParBERT’s
custom pattern memory and its
sequencer. External control SW
takes care of proper calibration
and test automation.
For more information:
www.agilent.com/find/pcie_
receiver_test
Reference
Clock Group
ParBERT Frame #1
Analyzer
Clock Group
N4809A
N4809A
Generator
Clock Group
ParBERT Frame #2
N4809A
33220A
Clk Out Clk Out
Clk In
Data Out Data Out
Data
In
Data In
Delay Delay
Ctrl In Ctrl In
Clk In Clk Out Clk Out Clk Out Clk Out
Data Out Data Out Data Out Data Out
Delay Delay Delay Delay
Ctrl In Ctrl In Ctrl In Ctrl In
ISI Board to DUT
33220A
100 MHz from DUT
Ref Clk
= 5 GHz Clock Signal
+ 75 GHz SSC Residual
= 2.5 GHz Clock Signal
= 11636B Power Divider
RJ Filter
Board
81150A
Figure 19. Example measurement set-up for a PCIe™ RX test with 4 data lanes
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