81250 Datasheet, PDF (5/64 Pages) Keysight Technologies – Agilent ParBERT 81250 Parallel Bit Error Ratio Tester

Table 1, a selection guide,
lists the maximum number
of channels per speed class
together with some features or
key specifications such as user
memory depth or input / output
voltage level ranges.
Multiple users at the same time
The ParBERT 81250 Hardware is
controlled by the ParBERT user
SW via an IEEE 1394 firewire
link. The SW is running on
an external PC. It consists of
three parts:
A firmware server and two
clients, the graphical user
interface (GUI) which allows
instrument setup and basic
(BER-) measurements and the
measurement user interface
(MUI) which provides a variety
of parametric physical layer
measurements based on BER-
measurements. GUI and MUI can
either run on the PC which hosts
the firmware server and controls
the HW or on any other PC which
is connected (e.g. via LAN) to
that PC mentioned above. They
control measurements on any of
the installed clock groups. Each
clock group can be controlled
by a different user. Plug&Play
drivers simplify controlling
ParBERT 81250 through Agilent
VEE, C/C++ or Visual Basic
programs or by SCPI based
language via GPIB.
Table 1. Brief selection guide for ParBERT 81250
Selection Guide for ParBERT 81250
target Data rate range
333.334 kb/s to
675 Mb/s
Data module back-ends
E4832A
Generator front ends
E4838A
Analyzer front ends
E4835A
Generator modules
N/A
Analyzer modules
N/A
Compatible clock
modules
E4805B/E4808A/
E4809A
Max. number of channels¹,
1 frame / 3 frames
44 / 132
adressed I/O technology
LVDS, PECL,
ECL, TTL, 3.3V
CMOS
Data capability
PRWS/PRBS
user memory
2 Mb
Input / Output
differential &
single ended
Data format
RZ, R1, NRZ, DNRZ
transition times 20%-80%
0.5-4.5ns, var
(10-90%)
amplitude resolution
0.1-3.5V, 10mV
window
-2.2 to 4V
input voltage ranges
0 to 5V -2 to 3V
sensitivity
sample delay resolution
50mV typ., diff.
2ps
20.834 Mb/s to
3.35 Gb/s
E4861A
E4862A
E4863A
N/A
N/A
E4808A/E4809A
22 / 66
LVDS, CML,
PECL, ECL,
low voltage CMOS
PRWS/PRBS
16 Mb
differential &
single ended
RZ, R1, NRZ, DNRZ
<75ps
0.05V-1.8V, 10mV
-2 to 3.5V
-2 to 1V, -1 to
2V, 0 to 3V
<50mV
1ps
620 Mb/s to
7 Gb/s,
N/A
N/A
N/A
N4874A
N4875A
E4809A
10 / 30
LVDS, CML,
PECL, ECL,
low voltage CMOS
PRWS/PRBS
64 Mb
differential &
single ended
NRZ, DNRZ
<20ps
0.1 1.8V, 5mV
-2 to 3V
-2 to 3V, 2Vpp
<50mV
100fs
620 Mb/s to
13.5 Gb/s
N/A
N/A
N/A
N4872A
N4873A
E4809A
10 / 30
LVDS, CML,
PECL, ECL,
low voltage CMOS
PRWS/PRBS
64 Mb
differential &
single ended
NRZ, DNRZ
<20ps
0.1 1.8V, 5mV
-2 to 3V
-2 to 3V, 2Vpp
<50mV
100fs
1. ParBERT 81250 controlled via IEEE 1394 link and external PC
ParBERT 81250 Main Overview
Page 5/64