81250 Datasheet, PDF (6/64 Pages) Keysight Technologies – Agilent ParBERT 81250 Parallel Bit Error Ratio Tester

Key features
Parallel BER measurements up
to 13.5 Gb/s
For characterization of parallel
or multi-lane interfaces ParBERT
81250 can generate and analyze
data clock-synchronously.
However, generator skew and
analyzer sample point timing can
be programmed independently
per channel as well as generator
levels or analyzer thresholds.
The BER is reported per lane
and port (see figure 2).
Figure 2. BER results screen
PRBS/PRWS and user
defined patterns
A common test pattern for serial
(communication) links is a Pseudo
Random Binary Sequence PRBS.
To simplify Mux/DeMux testing
ParBERT provides the so-called
Pseudo-Random-Word Sequences
(PRWS) for generation and as
expected data for analysis. A
PRWS consists of a PRBS per lane
with a lane-to-lane delay chosen
such that, when muxed together,
the same PRBS-polynomial as on
each lane of the parallel side is
generated on the serial side.
The appropriate lane-to-lane
delay is determined by the
number of lanes (see figure 3).
In addition, ParBERT’s pattern
memory enables user defined
test patterns as well.
Figure 3. MUX/DEMUX application:
relationship between PRBS and PRWS
Figure 4. Mechanism of auto-phase and
auto-delay assignment
Pattern sequencer
Physical layer testing includes
the establishment or termination
of a connection or the set-up of a
DUT into a specific test mode, e.g.
a loop-back of received data.
Furthermore, specific device
parameters often correlate with
suitable test patterns. To perform
such complex tests in one shot
without interruption to download
different test patterns, the
ParBERT 81250 is equipped with
a powerful pattern sequencer
Figure 5. ParBERT detail mode sequence editor screen
allowing up to five nested loops
and branching on internal and
external events or upon SW
command.
Set-up is made easy through the
powerful ParBERT 81250 graphical
sequence editor, which also aids
you maneuvering around HW
restrictions when setting up user
patterns not directly matching
selected block lengths. Debugging
of the test sequence is supported
e.g. by highlighting the currently
executed block within the
sequence (see figure 5).
Combining sequencing and
precise timing with internal or
external generator channel-add
allows realization of e.g.
user defined multi-level
or de-emphasized signals.
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ParBERT 81250⁶Main Overview