81250 Datasheet, PDF (40/64 Pages) Keysight Technologies – Agilent ParBERT 81250 Parallel Bit Error Ratio Tester

Table 46. Data rate range, segment length resolution, available memory for synchronization and
fine delay operation
Data rate range
Mb/s
20.834 ... 41.666
20.834 ... 82.333
20.834 ... 166.666
20.834 ... 333.333
20.834 ... 666.666
20.834 ... 1,333.333
20.834 ... 2,700.000
20.834 ... 3,350.000
Segment
length
1 bit
2 bits
4 bits
8 bits
16 bits
32 bits
64 bits
128 bits
Maximum memory
resolution depth, bits
131,072
262,144
524,288
1,048,576
2,097,152
4,194,304
8,388,608
16,777,216
Table 47. Dependancy of PRWS generation and port width.
Almost all the combinations are possible except the following:
PRWS
Port width
2⁷ - 1
No restriction
2⁹- 1
7
2¹⁰- 1
3, 11, 31, 33
2¹¹- 1
23
2¹⁵- 1
7, 31
2²³- 1
47
2³¹- 1
No restriction
Pattern generation
The data stream is composed of
segments. A segment can be a
memory-based pattern, memory-
based PRBS or hardware gener-
ated PRBS. A total of 16 Mbit
(at segment length resolution 128
bits) are available for memory-
based pattern and PRBS.
Memory-based PRBS is limited to
2¹⁵ - 1 or shorter. Memory-based
PRBS allows special PRBS modes
like zero substitution (also
known as extended zero run) and
variable mark ratio. A zero sub-
stitution pattern extends the
longest zero series by a user-
selectable number of additional
zeros. The next bit following
these zero-series will be forced to
1. Mark ratio is the ratio of ones
and zeros in a PRBS stream,
which is 1/2 in a normal PRBS.
Variable mark ratio allows values
of 1/8, 1/4, 1/2, 3/4, 7/8. Due to
granularity reasons a PRBS has
to be written to RAM several
times, at a multiplexing factor of
128 the number of repetitions is
also 128. That means that a 2¹⁵ - 1
PRBS uses up to 4 Mbit of the
memory. Hardware-based PRBS
can be any polynomial up to
2³¹ - 1. No memory is used, so the
total memory is free for memory-
based pattern generation. Error
insertion allows inserting single
or multiple errors into a data
stream. So instead of a ‘0’ a ‘1’ is
generated and vice versa. Single
errors can be inserted by pod or
via instruction from the central
sequencer. The user can trigger
an error with a signal supplied
to the qualifier pod of the central
module. An error insertion with
a fixed rate and a fixed distribu-
tion is supported. The user soft-
ware allows the selection of
errored and error-free segments.
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