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ISL6323B Datasheet, PDF (30/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors
ISL6323B
.
R1
=
RFB
⋅ ------------C------⋅---E----S-----R-------------
L ⋅ C – C ⋅ ESR
C1
=
-----L-----⋅---C-----–-----C------⋅---E----S-----R--
RFB
C2
=
--------------------------------------0----.-7----5-----⋅---V----I--N----------------------------------------
(2 ⋅ π)2 ⋅ f0 ⋅ fHF ⋅ ( L ⋅ C) ⋅ RFB ⋅ VP-P
RC
=
-V----P-------P-----⋅---⎝⎛--2----π---⎠⎞----2----⋅---f--0----⋅---f--H----F-----⋅---L-----⋅---C------⋅---R----F----B--
0.75 ⋅ VIN ⋅ (2 ⋅ π ⋅ fHF ⋅ L ⋅ C–1)
(EQ. 52)
CC
=
-------0----.-7----5----⋅---V-----I--N-----⋅---(--2-----⋅---π-----⋅---f--H----F-----⋅-------L-----⋅---C-----–---1----)-------
(2 ⋅ π)2 ⋅ f0 ⋅ fHF ⋅ ( L ⋅ C) ⋅ RFB ⋅ VP-P
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 53, RFB is selected arbitrarily. The remaining
compensation components are then selected according to
Equation 53.
In Equation 53, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and VPP is the peak-to-
peak sawtooth signal amplitude as described in Electrical
Specifications on page 6.
Case 1:
---------------1----------------
2⋅π⋅ L⋅C
>
f0
RC = RFB ⋅ 2-----⋅---π-----⋅---f-0-0--.--6⋅---6V-----P⋅---V---P--I--N-⋅-------L-----⋅---C---
CC
=
--------------0---.--6---6-----⋅---V----I--N----------------
2 ⋅ π ⋅ VPP ⋅ RFB ⋅ f0
Case 2:
---------------1----------------
2⋅π⋅ L⋅C
≤
f0
<
2-----⋅---π-----⋅---C--1----⋅---E----S-----R---
RC
=
RF
B
⋅
V-----P------P-----⋅---(--2-----⋅---π----)--2-----⋅----f--0--2----⋅----L-----⋅---C--
0.66 ⋅ VIN
CC
=
------------------------------0----.-6----6-----⋅---V----I--N--------------------------------
(2 ⋅ π)2 ⋅ f02 ⋅ VPP ⋅ RFB ⋅ L ⋅ C
(EQ. 53)
Case 3:
f0 > 2-----⋅---π-----⋅---C--1----⋅---E----S-----R---
RC = RFB ⋅ 2-0----.⋅-6--π--6----⋅-⋅--f--V0----I⋅--N-V----⋅P---E----P-S----⋅-R--L-
CC
=
-----0----.-6----6----⋅---V-----I-N------⋅---E----S-----R-----⋅--------C-------
2 ⋅ π ⋅ VP-P ⋅ RFB ⋅ f0 ⋅ L
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, ΔI,
the load-current slew rate, di/dt, and the maximum allowable
output-voltage deviation under transient loading, ΔVMAX.
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total
output-voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
as shown in Equation 54
ΔV
≈
ESL
⋅
-d---i
dt
+
ESR
⋅
ΔI
(EQ. 54)
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔVMAX.
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see “Interleaving” on
page 11 and Equation 3), a voltage develops across the bulk
capacitor ESR equal to IC(P-P ) (ESR). Thus, once the output
capacitors are selected, the maximum allowable ripple
voltage, VP-P(MAX), determines the lower limit on the
inductance..
L
≥ ESR ⋅
⎛
⎝
VIN
–
N
⋅
V O U T⎠⎞
⋅
VOUT
--------f--S-----⋅---V----I--N-----⋅---V----P-------P---(--M-----A----X----)-------
(EQ. 55)
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
30
FN6879.0
March 23, 2009