ISL6323B Datasheet, PDF (22/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323B
OUTPUT PRECHARGED
ABOVE DAC LEVEL
OUTPUT PRECHARGED
BELOW DAC LEVEL
V_CORE
400mV/DIV
EN
5V/DIV
100µs/DIV
FIGURE 14. SOFT-START WAVEFORMS FOR
ISL6323B-BASED MULTI-PHASE CONVERTER
Fault Monitoring and Protection
The ISL6323B actively monitors both CORE and NB output
voltages and currents to detect fault conditions. Fault
monitors trigger protective measures to prevent damage to
either load. One common power good indicator is provided
for linking to external system monitors. The schematic in
Figure 15 outlines the interaction between the fault monitors
and the power good signal.
Power-Good Signal
The power-good pin (VDDPWRGD) is an open-drain logic
output that signals whether or not the ISL6323B is regulating
both NB and CORE output voltages within the proper levels,
and whether any fault conditions exist. This pin should be
tied to a +5V source through a resistor.
During shutdown and soft-start, VDDPWRGD pulls low and
releases high after a successful soft-start and both output
voltages are operating between the undervoltage and
overvoltage limits. PGOOD transitions low when an
undervoltage, overvoltage, or overcurrent condition is detected
on either regulator output or when the controller is disabled by a
POR reset or EN. In the event of an overvoltage or overcurrent
condition, the controller latches off and PGOOD will not return
high. Pending a POR reset of the ISL6323B and successful
soft-start, the PGOOD will return high.
Overvoltage Protection
The ISL6323B constantly monitors the sensed output voltage
on the VSEN pin to detect if an overvoltage event occurs.
When the output voltage rises above the OVP trip level and
exceeds the PGOOD OV limit actions are taken by the
ISL6323B to protect the microprocessor load.
At the inception of an overvoltage event, both on-board lower
gate pins are commanded low as are the active PWM outputs
to the external drivers, the PGOOD signal is driven low, and the
ISL6323B latches off normal PWM action. This turns on the all
of the lower MOSFETs and pulls the output voltage below a
level that might cause damage to the load. The lower
MOSFETs remain driven ON until VDIFF falls below 400mV.
The ISL6323B will continue to protect the load in this fashion as
long as the overvoltage condition recurs. Once an overvoltage
condition ends the ISL6323B latches off, and must be reset by
toggling POR, before a soft-start can be re-initiated.
100µA
I_NB
-
OCP
+
NB ONLY
-
OCL
+
142µA
I₁
REPEAT FOR EACH
CORE CHANNEL
-
OCP
+
100µA
I_AVG
CORE ONLY
SOFT-START, FAULT
AND CONTROL LOGIC
NB ONLY
1.8V
+
OVP
-
ISEN_NB+
DAC - 300mV
CORE ONLY
1.8V
DAC + 250mV
-
UV
+
+
OVP
-
-
OV
+
VDDPWRGD
VSEN
DAC - 300mV
-
UV
+
ISL6323B INTERNAL CIRCUITRY
FIGURE 15. POWER-GOOD AND PROTECTION CIRCUITRY
Pre-POR Overvoltage Protection
Prior to PVCC and VCC exceeding their POR levels, the
ISL6323B is designed to protect either load from any
overvoltage events that may occur. This is accomplished by
means of an internal 10kΩ resistor tied from PHASE to
LGATE, which turns on the lower MOSFET to control the
output voltage until the overvoltage event ceases or the input
power supply cuts off. For complete protection, the low side
MOSFET should have a gate threshold well below the
maximum voltage rating of the load/microprocessor.
In the event that during normal operation the PVCC or VCC
voltage falls back below the POR threshold, the pre-POR
overvoltage protection circuitry reactivates to protect from
any more pre-POR overvoltage events.
22
FN6879.0
March 23, 2009