ISL6323B Datasheet, PDF (29/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323B
C₂ (OPTIONAL)
R_C ^CC
COMP
FB
ISL6323B
R_FB
VSEN
FIGURE 22. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6323B CIRCUIT
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the L-C
poles and the ESR zero of the voltage mode approximation,
yields a solution that is always stable with very close to ideal
transient performance.
Select a target bandwidth for the compensated system, f₀.
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f₀
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
In Equation 51, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent series resistance of
the bulk output filter capacitance; and V_PP is the
peak-to-peak sawtooth signal amplitude as described in the
Electrical Specifications on page 6.
Once selected, the compensation values in Equation 51
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R_C. Slowly increase the
value of R_C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C_C will not need adjustment. Keep the value of C_C from
Equation 51 unless some performance issue is noted.
The optional capacitor C₂, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 22). Keep
a position available for C₂, and be prepared to install a
high-frequency capacitor of between 22pF and 150pF in
case any leading edge jitter problem is noted.
Case 1:
---------------1----------------
2⋅π⋅ L⋅C
>
f₀
R_C
=
R_FB ⋅
2-----⋅_---π_-----⋅_---f--0----⋅_{---V-----P------P-----}⋅_{-------L-----}⋅_---C---
0.66 ⋅ V_IN
C_C
=
--------------0---.--6---6-----^â‹---V----^I--^N----------------
2 ⋅ π ⋅ V_PP ⋅ R_FB ⋅ f₀
Case 2:
---------------1----------------
2⋅π⋅ L⋅C
≤
f₀
<
2-----⋅^---π^-----⋅^---C--1----⋅^{---E----S-----R---}
R_C = R_FB ⋅ ^V-----P---^---^P-----^â‹---⁽--02---.--6^â‹---^π_6----⁾-_â‹-²---V--^â‹---_I-f-_N-⁰--²----^â‹----L-----^â‹---C--
C_C
=
------------------------------0----.-6----6-----^â‹---V----^I--^N--------------------------------
(2 ⋅ π)² ⋅ f₀₂ ⋅ V_PP ⋅ R_FB ⋅ L ⋅ C
(EQ. 51)
Case 3:
f₀
>
------------------1-------------------
2 ⋅ π ⋅ C ⋅ ESR
R_C = R_FB ⋅ ^2-0---.-â‹-6--^π-6-----^â‹-_â‹--f--V⁰----_I^â‹--_N-V----_â‹^P---E-^---^P-S----^â‹-R--L-
C_C
=
-----0----.-6----6----^â‹---V-----^I-^N------^â‹---E----S-----R-----^â‹--------C-------
2 ⋅ π ⋅ V_P-P ⋅ R_FB ⋅ f₀ ⋅ L
Compensation Without Loadline Regulation
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
type III controller, as shown in Figure 23, provides the
necessary compensation.
The first step is to choose the desired bandwidth, f₀, of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than 1/3
of the switching frequency. The type-III compensator has an
extra high-frequency pole, f_HF. This pole can be used for added
noise rejection or to assure adequate attenuation at the error-
amplifier high-order pole and zero frequencies. A good general
rule is to choose f_HF = 10f₀, but it can be higher if desired.
Choosing f_HF to be lower than 10f₀ can cause problems with
too much phase shift below the system bandwidth.
C₂
R_C ^CC
COMP
C₁
R₁
R_FB
FB
ISL6323B
VSEN
FIGURE 23. COMPENSATION CIRCUIT WITHOUT LOAD-LINE
REGULATION
29
FN6879.0
March 23, 2009