ISL6323B Datasheet, PDF(24/35 Page) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

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ISL6323B Datasheet, PDF (24/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

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ISL6323B

OVERCURRENT PROTECTION IN POWER SAVINGS

MODE

While in Power Savings Mode, the OCP trip point will be

lower than when running in Normal Mode. Equation 20, with

N = 1, will yield the OCP trip point for the Core regulator

while in Power Savings mode.

If an overcurrent event should occur while the system is in

Power Savings Mode, the ISL6323B will restart in the

Normal state with the PSI_L bit set to 1.

Individual Channel Overcurrent Limiting

The ISL6323B has the ability to limit the current in each

individual channel of the Core regulator without shutting

down the entire regulator. This is accomplished by

continuously comparing the sensed currents of each channel

with a constant 140ÂµA OCL reference current. If a channelâs

individual sensed current exceeds this OCL limit, the UGATE

signal of that channel is immediately forced low, and the

LGATE signal is forced high. This turns off the upper

MOSFET(s), turns on the lower MOSFET(s), and stops the

rise of current in that channel, forcing the current in the

channel to decrease. That channelâs UGATE signal will not

be able to return high until the sensed channel current falls

back below the 140ÂµA reference.

General Design Guide

This design guide is intended to provide a high-level

explanation of the steps necessary to create a multiphase

power converter. It is assumed that the reader is familiar with

many of the basic skills and techniques referenced below. In

addition to this guide, Intersil provides complete reference

designs that include schematics, bills of materials, and example

board layouts for all common microprocessor applications.

Power Stages

The first step in designing a multiphase converter is to

determine the number of phases. This determination depends

heavily on the cost analysis which in turn depends on system

constraints that differ from one design to the next. Principally,

the designer will be concerned with whether components can

be mounted on both sides of the circuit board, whether

through-hole components are permitted, the total board space

available for power-supply circuitry, and the maximum amount

of load current. Generally speaking, the most economical

solutions are those in which each phase handles between

25A and 30A. All surface-mount designs will tend toward the

lower end of this current range. If through-hole MOSFETs and

inductors can be used, higher per-phase currents are

possible. In cases where board space is the limiting

constraint, current can be pushed as high as 40A per phase,

but these designs require heat sinks and forced air to cool the

MOSFETs, inductors and heat-dissipating surfaces.

MOSFETS

The choice of MOSFETs depends on the current each

MOSFET will be required to conduct, the switching frequency,

the capability of the MOSFETs to dissipate heat, and the

availability and nature of heat sinking and air flow.

LOWER MOSFET POWER CALCULATION

The calculation for power loss in the lower MOSFET is

simple, since virtually all of the loss in the lower MOSFET is

due to current conducted through the channel resistance

(rDS(ON)). In Equation 21, IM is the maximum continuous

output current, IP-P is the peak-to-peak inductor current

(see Equation 2), and d is the duty cycle (VOUT/VIN).

PLOW, 1 = rDS(ON) â

I--M---ââ

Nâ

(

)

I--L---,---2P----P-----â---(--1-----â-----d----)

(EQ. 21)

An additional term can be added to the lower-MOSFET loss

equation to account for additional loss accrued during the

dead time when inductor current is flowing through the

lower-MOSFET body diode. This term is dependent on the

diode forward voltage at IM, VD(ON), the switching

frequency, fS, and the length of dead times, td1 and td2, at

the beginning and the end of the lower-MOSFET conduction

interval respectively.

PLOW, 2

VD(ON) â fS â

I--M----

I--P-------P---ââ

âN 2 â

td1

I--M----

I--P---2----P---â âââ

td2

(EQ. 22)

The total maximum power dissipated in each lower MOSFET

is approximated by the summation of PLOW,1 and PLOW,2.

UPPER MOSFET POWER CALCULATION

In addition to rDS(ON) losses, a large portion of the upper-

MOSFET losses are due to currents conducted across the

input voltage (VIN) during switching. Since a substantially

higher portion of the upper-MOSFET losses are dependent on

switching frequency, the power calculation is more complex.

Upper MOSFET losses can be divided into separate

components involving the upper-MOSFET switching times,

the lower-MOSFET body-diode reverse-recovery charge, Qrr,

and the upper MOSFET rDS(ON) conduction loss.

When the upper MOSFET turns off, the lower MOSFET does

not conduct any portion of the inductor current until the

voltage at the phase node falls below ground. Once the

lower MOSFET begins conducting, the current in the upper

MOSFET falls to zero as the current in the lower MOSFET

ramps up to assume the full inductor current. In Equation 23,

the required time for this commutation is t1 and the

approximated associated power loss is PUP,1.

PUP,1 â VIN

-I-M---

I--P--2-----P--â â

-t-1--

â 2â

â fS

(EQ. 23)

At turn on, the upper MOSFET begins to conduct and this

transition occurs over a time t2. In Equation 24, the

approximate power loss is PUP,2.

PUP, 2

VIN

I--M---

âN

I--P-------P--ââ

2â

-t-2--

2â

(EQ. 24)

FN6879.0

March 23, 2009

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