ISL6323B Datasheet, PDF (21/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323B
Detect block, the external driver POR checking is supported
by the Enable Comparator.
Enable Comparator
The ISL6323B features a dual function enable input (EN) for
enabling the controller and power sequencing between the
controller and external drivers or another voltage rail. The
enable comparator holds the ISL6323B in shutdown until the
voltage at EN rises above 0.86V. The enable comparator has
about 110mV of hysteresis to prevent bounce. It is important
that the driver ICs reach their rising POR level before the
ISL6323B becomes enabled. The schematic in Figure 12
demonstrates sequencing the ISL6323B with the ISL66xx
family of Intersil MOSFET drivers, which require 12V bias.
When selecting the value of the resistor divider the driver
maximum rising POR threshold should be used for calculating
the proper resistor values. This will prevent improper
sequencing events from creating false trips during soft-start.
If the controller is configured for 2-phase CORE operation,
then the resistor divider can be used for sequencing the
controller with another voltage rail. The resistor divider to EN
should be selected using a similar approach as the previous
driver discussion.
The EN pin is also used to force the ISL6323B into either
PVI or SVI mode. The mode is set upon the rising edge of
the EN signal. When the voltage on the EN pin rises above
0.86V, the mode will be set depending upon the status of the
VID1/SEL pin.
Phase Detection
The ISEN3- and ISEN4- pins are monitored prior to soft-start
to determine the number of active CORE channel phases.
If ISEN4- is tied to VCC, the controller will configure the
channel firing order and timing for 3-phase operation. If
ISEN3- and ISEN4- are tied to VCC, the controller will set
the channel firing order and timing for 2-phase operation
(see “PWM Operation” on page 13 for details).
Soft-Start Output Voltage Targets
Once the POR and Phase Detect blocks and enable
comparator are satisfied, the controller will begin the
soft-start sequence and will ramp the CORE and NB output
voltages up to the SVI interface designated target level if the
controller is set SVI mode. If set to PVI mode, the North
Bridge regulator is disabled and the core is soft started to the
level designated by the parallel VID code.
SVI Mode
Prior to soft-starting both CORE and NB outputs, the
ISL6323B must check the state of the SVI interface inputs to
determine the correct target voltages for both outputs. When
the controller is enabled, the state of the VFIXEN, SVD and
SVC inputs are checked and the target output voltages set
for both CORE and NB outputs are set by the DAC (see
“Serial VID Interface (SVI)” on page 15). These targets will
only change if the EN signal is pulled low or after a POR
reset of VCC.
Soft-Start
The soft-start sequence is composed of three periods, as
shown in Figure 13. At the beginning of soft-start, the DAC
immediately obtains the output voltage targets for both outputs
by decoding the state of the SVI or PVI inputs. A 100µs fixed
delay time, TDA, proceeds the output voltage rise. After this
delay period the ISL6323B will begin ramping both CORE and
NB output voltages to the programmed DAC level at a fixed rate
of 3.25mV/µs. The amount of time required to ramp the output
voltage to the final DAC voltage is referred to as TDB, and can
be calculated as shown in Equation 19.
TDB
=
--------^V----^D----^A----^C----------
3.25 × 10^–3
(EQ. 19)
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high.
V_NB
400mV/DIV
V_CORE
400mV/DIV
EN
5V/DIV
TDA
TDB
VDDPWRGD
5V/DIV
100µs/DIV
FIGURE 13. SOFT-START WAVEFORMS
Pre-Biased Soft-Start
The ISL6323B also has the ability to start up into a
pre-charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output
to ramp from the pre-charged level to the final level dictated
by the DAC setting. Should the output be pre-charged to a
level exceeding the DAC setting, the output drives are
enabled at the end of the soft-start period, leading to an
abrupt correction in the output voltage down to the DAC-set
level. Both CORE and NB output support start up into a
pre-charged output.
21
FN6879.0
March 23, 2009