ISL6323B Datasheet, PDF (23/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323B
Undervoltage Detection
The undervoltage threshold is set at VDAC - 300mV typical.
When the output voltage (VSEN-RGND) is below the
undervoltage threshold, PGOOD gets pulled low. No other
action is taken by the controller. PGOOD will return high if
the output voltage rises above VDAC - 250mV typical.
Open Sense Line Protection
In the case that either of the remote sense lines, VSEN or
GND, become open, the ISL6323B is designed to detect this
and shut down the controller. This event is detected by
monitoring small currents that are fed out the VSEN and RGND
pins. In the event of an open sense line fault, the controller will
continue to remain off until the fault goes away, at which point
the controller will re-initiate a soft-start sequence.
Overcurrent Protection
The ISL6323B takes advantage of the proportionality between
the load current and the average current, I_AVG, to detect an
overcurrent condition. See “Continuous Current Sampling” on
page 13 and “Channel-Current Balance” on page 14 for more
detail on how the average current is measured. Once the
average current exceeds 100µA, a comparator triggers the
converter to begin overcurrent protection procedures. The
Core regulator and the North Bridge regulator have the same
type of overcurrent protection.
The overcurrent trip threshold is dictated by the DCR of the
inductors, the number of active channels, the DC gain of the
inductor RC filter and the R_SET resistor. The overcurrent trip
threshold is shown in Equation 20.
I_OCP
=
100 μ A
⋅
-----^N--------
DCR
⋅
-¹--
K
⋅
⎛
⎝
----³-----
400
⋅
R _{S E T⎠⎞}
–
-^V----^I--^N-----–----^N------^â‹---^V----^O-----^U----^T--
2 ⋅ L ⋅ f_S
⋅
-^V----^O----^U----^T--
V_IN
(EQ. 20)
Where:
K = -------^R-----²--------
R₁ + R₂
See “Continuous Current Sampling” on
page 13.
f_SW = Switching Frequency
Equation 20 is valid for both the Core regulator and the
North Bridge regulator. This equation includes the DC load
current as well as the total ripple current contributed by all
the phases. For the North Bridge regulator, N is 1.
During soft-start, the overcurrent trip point is boosted by a factor
of 1.4. Instead of comparing the average measured current to
100µA, the average current is compared to 140µA. Immediately
after soft-start is over, the comparison level changes to 100µA.
This is done to allow for start-up into an active load while still
supplying output capacitor in-rush current.
CORE REGULATOR OVERCURRENT
At the beginning of overcurrent shutdown, the controller sets all
of the UGATE and LGATE signals low, puts PWM3 and PWM4
(if active) in a high-impedance state, and forces VDDPWRGD
low. This turns off all of the upper and lower MOSFETs. The
system remains in this state for fixed period of 12ms. If the
controller is still enabled at the end of this wait period, it will
attempt a soft-start, as shown in Figure 16. If the fault remains,
the trip-retry cycles will continue until either the fault is cleared
or for a total of seven attempts. If the fault is not cleared on the
final attempt, the controller disables UGATE and LGATE
signals for both Core and North Bridge and latches off requiring
a POR of VCC to reset the ISL6323B.
OUTPUT CURRENT, 50A/DIV
0A
OUTPUT VOLTAGE,
500mV/DIV
0V
3ms/DIV
FIGURE 16. OVERCURRENT BEHAVIOR IN HICCUP MODE
It is important to note that during soft start, the overcurrent
trip point is increased by a factor of 1.4. If the fault draws
enough current to trip overcurrent during normal run mode, it
may not draw enough current during the soft start ramp
period to trip overcurrent while the output is ramping up. If a
fault of this type is affecting the output, then the regulator will
complete soft start and the trip-retry counter will be reset to
zero. Once the regulator has completed soft start, the
overcurrent trip point will return to it’s nominal setting and an
overcurrent shutdown will be initiated. This will result in a
continuous hiccup mode.
Note that the energy delivered during trip-retry cycling is
much less than during full-load operation, so there is no
thermal hazard.
NORTH BRIDGE REGULATOR OVERCURRENT
The overcurrent shutdown sequence for the North Bridge
regulator is identical to the Core regulator with the exception
that it is a single phase regulator and will only disable the
MOSFET drivers for the North Bridge. Once 7 retry attempts
have been executed unsuccessfully, the controller will disable
UGATE and LGATE signals for both Core and North Bridge and
will latch off requiring a POR of VCC to reset the ISL6323B.
Note that the energy delivered during trip-retry cycling is
much less than during full-load operation, so there is no
thermal hazard.
23
FN6879.0
March 23, 2009