ISL6323B Datasheet, PDF (3/35 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6323B
Controller Block Diagram
RGND_NB
FB_NB
COMP_NB
ISEN_NB+
ISEN_NB-
VDDPWRGD
APA
COMP
OFS
FB
DVC
RGND
PWROK
VID0/VFIXEN
VID1/SEL
VID2/SVD
VID3/SVC
VID4
VID5
VSEN
RSET
ISEN1+
ISEN1-
ISEN2+
ISEN2-
ISEN3+
ISEN3-
ISEN4+
ISEN4-
NB_REF _∑
CURRENT
SENSE
UV
LOGIC
OV
LOGIC
E/A
RAMP
MOSFET
DRIVER
APA
OFFSET
E/A
2X
∑
SVI
SLAVE
BUS
AND
PVI
DAC
NB
FAULT
LOGIC
SOFT-START
AND
FAULT LOGIC
EN_12V
ENABLE
LOGIC
POWER-ON
RESET
LOAD APPLY
TRANSIENT
ENHANCEMENT
CLOCK AND
TRIANGLE WAVE
GENERATOR
DROOP
CONTROL
MOSFET
DRIVER
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
PVCC_NB
EN
VCC
PVCC1_2
BOOT1
UGATE1
PHASE1
LGATE1
FS
NB_REF
OV
LOGIC
UV
LOGIC
RESISTOR
MATCHING
CH1
CURRENT
SENSE
∑
∑
OC
I_TRIP I_AVG
∑
∑
PWM1
PWM2
PWM3
PWM4
CH2
CURRENT
SENSE
CH3
CURRENT
SENSE
ISEN3-
CH4
CURRENT
SENSE
ISEN4-
CHANNEL
CURRENT
BALANCE
I_AVG ₁
N
∑
GND
MOSFET
DRIVER
PH3/PH4
POR
CHANNEL
DETECT
EN_12V
ISEN3-
ISEN4-
BOOT2
UGATE2
PHASE2
LGATE2
PWM3
SIGNAL
LOGIC
PWM4
SIGNAL
LOGIC
PWM3
PWM4
3
FN6879.0
March 23, 2009